3D Stacked Memory Cell Pillars for Neuromorphic Data Storage
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Solution Overview
Problem
Current 3D stacked semiconductor memory devices and neuromorphic technologies face challenges in achieving multiple resistance levels and efficient data storage and processing, particularly in implementing cross-point connections with variable resistance layers that effectively mimic the human brain's synaptic functions for advanced AI applications.
Innovation Solution
The semiconductor memory device incorporates a 3D stacked structure with multiple variable resistance layers, including metal oxides and high-k oxides with oxygen vacancies, arranged in a cross-point configuration, where cell pillars with a central core and surrounding memory layers are electrically coupled to row and column lines, allowing for varying resistance levels based on voltage differences and filament formation thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3D stacked structure with multiple variable resistance layers is implemented, then multiple resistance levels and data storage capacity are improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple variable resistance layers (first variable resistance layer, second variable resistance layer, third variable resistance layer) stacked vertically, with each layer contributing to the overall resistance state. This segmentation allows multiple resistance levels to be achieved through different combinations of layer states, effectively increasing data storage capacity while maintaining manageable complexity through modular design
Solution Approach 2:
The patent transitions from a planar 2D memory structure to a 3D stacked structure by adding the vertical dimension with multiple variable resistance layers stacked above each other. This dimensional change enables multiple bits of data to be stored in a single memory cell location by utilizing the resistance states of different layers, significantly increasing storage capacity without proportionally increasing device footprint or complexity
2Productivity
If cell pillars with central core and memory layers are used in cross-point configuration, then integration density and operating speed are improved, but manufacturing precision requirements increase
Solution Approach 1:
The cell pillar structure implements a nested configuration where the central core is surrounded by multiple variable resistance layers in a concentric arrangement. The first variable resistance layer is positioned between the central core and the second variable resistance layer, which is in turn surrounded by the third variable resistance layer. This nested structure enables high integration density by maximizing space utilization within the pillar volume while maintaining clear structural hierarchy that simplifies manufacturing processes
Solution Approach 2:
Different regions of the cell pillar are assigned different functional properties: the central core provides electrical connection and structural support, while the surrounding variable resistance layers provide memory storage functionality with different resistance characteristics. This local differentiation of quality allows each component to be optimized for its specific function, improving overall operating speed while managing manufacturing complexity through specialized fabrication processes for each region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the semiconductor memory device to achieve multiple resistance levels and efficient data storage and processing, enhancing the integration and operating speed of neuromorphic devices for advanced AI applications while maintaining low power consumption.
Implementation Method 1
variable resistance layers that have at least one different characteristics among energy band gaps, chemical potentials, ion mobilities, filament formation threshold voltages
Implementation Method 2
metal oxides or high dielectric constant (high-k) oxides containing oxygen vacancies
Data Source
AI summary
A semiconductor memory device may include: a plurality of row lines extended in parallel to each other in a first horizontal direction; a plurality of column line stacks extended in parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, wherein each of the plurality of column line stacks includes a plurality of column lines extended in parallel to each other in a vertical direction; and a plurality of cell pillars that pass vertically through the column lines of the column line stacks, each of the plurality of cell pillars has a first end and a second end, wherein the first ends of the plurality of cell pillars are electrically coupled to the plurality of row lines, and the second ends of the plurality of cell pillars are floated. Each cell pillar includes a core and variable resistance memory layers.