3D Stacked Nonvolatile Memory Source Potential Stabilization
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Solution Overview
Problem
The BiCS memory technology faces challenges in stabilizing the potential of the source diffusion layer due to its unique device structure, leading to unstable source potential during read operations, primarily because the contact area for the source diffusion layer is formed outside the memory cell array, causing floating of the source potential.
Innovation Solution
A three-dimensional stacked nonvolatile semiconductor memory design that includes contact plugs interposed between blocks in the memory cell array, connecting the source diffusion layer to a source line above the conductive layers, which stabilizes the source potential by forming a shunt area within the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the contact area of the source diffusion layer is formed outside of the memory cell array, then the memory cell array area is minimized, but the source potential becomes unstable due to resistance-induced floating
Solution Approach 1:
The patent transitions from a two-dimensional planar contact area to a three-dimensional vertical contact structure by forming contact holes through the insulating film and conductive layers down to the source diffusion layer. This vertical dimension allows the contact area to be positioned within the memory cell array footprint while maintaining electrical connection, thus resolving the contradiction between minimizing array area and stabilizing source potential.
Solution Approach 2:
The patent introduces an intermediary conductive structure (contact plug) that bridges the source diffusion layer and the source line through multiple insulating and conductive layers. This intermediary pathway provides a low-resistance connection that prevents potential floating, while the contact area can be optimally positioned within the memory cell array boundaries.
2Ease of manufacture
If the contact area is formed outside the memory cell array, then layout simplicity is maintained, but read operation reliability deteriorates due to source potential floating
Solution Approach 1:
By forming the contact area vertically within the stacked structure rather than laterally outside the array, the patent maintains layout compactness while achieving reliable electrical connection. The contact holes penetrate through insulating films and conductive layers to reach the source diffusion layer, providing a straightforward manufacturing process that does not complicate the overall layout.
3Device complexity
If the source diffusion layer contact area is positioned outside the memory cell array, then device structure complexity is reduced, but source potential stability is compromised
Solution Approach 1:
The contact structure is nested within the memory cell array stack, with the contact hole penetrating through multiple insulating and conductive layers to reach the source diffusion layer. This nested configuration integrates the contact area within the existing device structure without adding external complexity, while ensuring stable source potential through direct electrical connection.
Data Source
AI summary
A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. A source diffusion layer, which is common to the first and second blocks, is disposed in a semiconductor substrate, and a contact plug, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above at least three conductive layers, is interposed between the first and second blocks.