3D Stacked Phase Change Memory Using Photoresist Planarization
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Solution Overview
Problem
The manufacturing process of three-dimensional stacked phase change memory devices is complex, costly, and has a low yield rate due to complicated steps and increased crosstalk between units, leading to reliability issues and high unit costs.
Innovation Solution
A method involving the preparation of strip-shaped electrodes, insulating layers with through holes, and phase change material filling, using spin-coated photoresist for local planarization and etching to simplify the process while ensuring reliability, with repeated stacking to form a three-dimensional stacked memory structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional multi-layer hole etching and filling process is used for three-dimensional stacked memory, then storage density can be increased, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent segments the memory structure into multiple stacked layers, each containing phase change units formed by etching holes through insulating layers. This segmentation allows independent formation of each layer's memory units, enabling scalable three-dimensional stacking while maintaining manageable process complexity for each individual layer.
Solution Approach 2:
The patent transitions from two-dimensional planar memory to three-dimensional stacked memory by adding the vertical dimension. Multiple layers of phase change units are stacked vertically with insulating layers between them, dramatically increasing storage density without proportionally increasing lateral device footprint or process complexity.
2Quantity of substance
If feature size is reduced to increase integration density, then storage capacity improves, but crosstalk between units increases and leakage currents worsen
Solution Approach 1:
The patent applies local quality by using insulating layers with through-holes that provide localized electrical isolation between adjacent phase change units. This local insulation strategy effectively reduces crosstalk and leakage currents between neighboring units while allowing the overall device to achieve high integration density through compact unit spacing.
Solution Approach 2:
The insulating layers act as intermediary elements between adjacent phase change units and electrode layers. These intermediary layers provide electrical isolation and prevent direct interaction between conductive elements, thereby reducing crosstalk and leakage currents while enabling higher integration density through closer unit placement.
3Quantity of substance
If multiple-layer hole etching and filling is performed for each layer, then three-dimensional stacking is achieved, but manufacturing cost and process difficulty increase
Solution Approach 1:
The patent employs preliminary action by pre-forming insulating layers with through-holes using a standardized process before depositing electrode materials and phase change units. This preliminary preparation of the insulating layer structure simplifies subsequent manufacturing steps and enables consistent replication across multiple stacked layers, reducing overall process difficulty.
Solution Approach 2:
The patent utilizes parameter changes by varying the thickness of insulating layers between 50-200 nm and controlling through-hole dimensions and spacing to optimize both stacking capability and manufacturing ease. These parameter adjustments allow flexible adaptation of the process to different fabrication capabilities while maintaining effective three-dimensional stacking.
4Manufacturing precision
If CMP planarization process is applied for each layer, then manufacturing precision is maintained, but productivity decreases and cost increases
Solution Approach 1:
The patent extracts the CMP planarization step from the mandatory process sequence for each layer. Instead of performing CMP on every layer, the method selectively applies planarization only when necessary for subsequent processing steps, thereby maintaining manufacturing precision where required while significantly improving overall productivity and reducing manufacturing cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves storage density and reduces manufacturing costs by simplifying the process, increasing yield, and enhancing the reliability of the three-dimensional stacked memory devices.
Implementation Method 1
Spin-coating photoresist on the structure formed in step (5) as a sacrificial material
Implementation Method 2
using an etching process to perform a local planarization operation on the surface of the second insulating layer
Implementation Method 3
Through applying specific pulses to chalcogenide-based phase change materials, the phase change memory undergoes rapid transformation between ordered crystalline state (low resistance) and disordered crystalline state (high resistance)
Data Source
AI summary
The disclosure discloses a three-dimensional stacked memory and a preparation method thereof. The storage unit adopts a constrained structure phase change storage unit, and uses a crossbar storage array structure to build a large-capacity storage array. The preparation method includes: preparing N first strip-shaped electrodes along a crystal direction on a substrate; preparing a first insulating layer with M*N array of through holes; filling the M*N array of through holes of the first insulating layer with a phase change material to form first phase change units; preparing M second strip-shaped electrodes; preparing a second insulating layer, using spin-coated photoresist as a sacrificial material, performing a local planarization on the surface of the second insulating layer; forming M*N array of through holes on the second insulating layer; filling a phase change material to form second phase change units; preparing N third strip-shaped electrodes to form a two-layer stacked phase change memory.