3D Stacked Substrate Package for Dense High-Speed Interconnects
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Solution Overview
Problem
Conventional semiconductor packages face issues of excess cost, decreased reliability, and large package sizes, leading to inadequate performance.
Innovation Solution
The integration of high-density 3D interconnect configurations using substrate interposers in stacked or package-on-package configurations, incorporating photonic integrated circuits for optical signal processing, and multiple substrates to enhance integration and functionality, while supporting high-speed interfacing in a reduced body size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor packages are used, then manufacturing is simpler, but package size becomes too large
Solution Approach 1:
The patent transitions from conventional 2D planar packaging to 3D stacked packaging architecture. Multiple semiconductor dies are vertically stacked and interconnected through through-silicon vias (TSVs), enabling high-density interconnection in the vertical dimension. This dimensional change reduces the lateral footprint and overall package volume while accommodating complex interconnect structures.
Solution Approach 2:
The patent implements nested packaging where multiple semiconductor dies are stacked one on top of another, with each die containing functional circuits. The dies are nested within a common package substrate that provides mechanical support and electrical interconnection. This nesting approach maximizes space utilization and reduces package size.
2Quantity of substance
If conventional interconnection methods are used, then manufacturing is easier, but interconnection density is low
Solution Approach 1:
The patent employs three-dimensional vertical interconnection through TSVs that penetrate through the silicon substrate thickness. This vertical routing in the Z-dimension enables high-density interconnection between stacked dies, dramatically increasing the number of interconnects per unit area compared to conventional planar routing methods.
Solution Approach 2:
The patent divides the semiconductor package into multiple discrete functional dies that are separately manufactured and then stacked. Each die can be independently optimized and manufactured, allowing parallel production. The segmentation enables modular assembly and facilitates high-density interconnection through standardized interfaces between dies.
3Volume of moving object
If package size is reduced, then integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates alignment marks and reference structures during the die fabrication process. These preliminary features are built into each die before stacking, enabling precise alignment during the assembly process. The preliminary action of creating alignment references simplifies the subsequent stacking and bonding operations, maintaining manufacturing feasibility despite reduced package dimensions.
4Adaptability or versatility
If more substrates are integrated, then functionality is enhanced, but device complexity increases
Solution Approach 1:
The patent designs the package substrate to serve multiple functions simultaneously: mechanical support for stacked dies, electrical interconnection through TSVs, thermal management pathway, and alignment reference system. This multi-functionality reduces the need for separate dedicated structures, managing complexity while enhancing integration capabilities.
Solution Approach 2:
The patent combines multiple functional elements into integrated structures. For example, the package substrate integrates interconnect pathways, mechanical support features, and thermal conduction paths into a single unified component. This merging approach reduces the total number of discrete parts and simplifies the overall device architecture while maintaining enhanced functionality.
Data Source
AI summary
In one example, an electronic device includes a first substrate and a second substrate. The first substrate includes a substrate first side, a substrate second side, and a first conductive structure. An inner electronic component is coupled to the first conductive structure proximate to the substrate second side. An outer electronic component is coupled to the first conductive structure proximate to the substrate first side. The outer electronic component includes a body and a groove in the body configured to couple with an external interconnect. Inner interconnects couple the first substrate to the second substrate. The first substrate, the second substrate, the inner electronic component, and the outer electronic component are in a stacked configuration. The inner electronic component is interposed between the first substrate and the second substrate. Other examples and related methods are also disclosed herein.