3D Standard Cell Layout for Higher Logic Density CMOS

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Solution Overview

Problem

Conventional semiconductor devices face challenges in achieving high element density per substrate unit area due to the stacking of NMOS and PMOS transistors, which limits their performance in three-dimensional circuits.

Innovation Solution

The implementation of a semiconductor integrated circuit design that utilizes two types of standard cells with different numbers of layers, where the first CMOS circuit and second CMOS circuit are formed with a combination of PMOS and NMOS transistors, respectively, and share gate terminals in specific configurations to enhance logic density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If NMOS and PMOS transistors are stacked in three-dimensional circuits, then device miniaturization is achieved, but element density per substrate unit area remains low

Engineering Contradiction:

Improvedevice sizeVSAvoidelement density per substrate unit area

Core Design Contradiction:

Volume of moving objectVSQuantity of substance

Solution Approach 1:

The patent transitions from conventional planar (2D) circuit layouts to three-dimensional stacked configurations where multiple transistor layers are vertically arranged. By utilizing the vertical dimension for stacking NMOS and PMOS transistors in multiple layers, the design achieves higher element density per substrate unit area while maintaining miniaturization benefits

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested transistor structures where PMOS and NMOS transistors are interleaved in alternating layers. Each transistor layer is positioned within the vertical stack, with source/drain regions of one layer nested between the source/drain regions of adjacent layers, maximizing space utilization and element density

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS20240429224A1Semiconductor integrated circuit, layout design system, layout designing method, and non-transitory computer-readable storage medium storing program

Publication Date: 2024.12.26 KIOXIA CORP

AI summary

According to one embodiment, a semiconductor integrated circuit includes a first semiconductor layer stacked as a (2n−1)th layer, and a second semiconductor layer stacked as a (2n)th layer. The semiconductor integrated circuit further includes: a first standard cell in which a first conductivity type MOS as a (4i−1)th layer and a second conductivity type MOS as a (4i)th layer share a gate terminal; a second standard cell in which the first conductivity type MOS as a (4i−3)th layer and the second conductivity type MOS as a (4i−2)th layer share a gate terminal; and a third standard cell in which the first conductivity type MOSs as the (4i−3)th layer and as the (4i−1)th layer and the second conductivity type MOSs as the (4i)th layer and as the (4i−2)th layer shares a gate terminal.