Solid-State Devices TRIZ Cases

A dedicated bending area and directly connected dual-layer lines shrink bezel space while reducing crack risk in flexible electroluminescent displays.

An n-dopant electron extraction layer boosts photoelectric conversion in integrated display sensors for more accurate touch and biometric input.

A segmented sub-pixel and transmission-area layout preserves resolution and transmittance while freeing display space for integrated components.

A stepped buried gate cuts gate-drain overlap and capacitance, lowering amplified pixel noise in CMOS image sensor readout.

A resin-filled package structure covers bonding wires and processed substrate edges to improve heat dissipation while preventing flare and material fallout.

A high-boiling antioxidant coating protects Mini LED binding terminals during heat processing while preserving stable drive-assembly bonding.

Different display regions use tailored pixel and signal-line density to meet under-screen sensor transmittance needs without sacrificing display quality.

A three-zone pixel layout shifts from RGB to RG/BG to raise under-screen camera transmittance while smoothing boundary visibility.

Vertical edge-emitting LED stacking moves contacts away from the emitting edge, enabling fine-pitch arrays with better light efficiency and color quality.

An oxide film on the oxide semiconductor layer prevents oxygen loss, stabilizes energy levels, and preserves image sensor charge transfer.

Multiple contact pairs and backup wiring paths let Mini LED backlights cut power use, improve bonding yield, and recover from defective chips.

Shared signal-line placement between adjacent photoelectric elements raises aperture ratio while keeping pixel pitch uniform for accurate detection.

A mixed first- and second-pixel layout equalizes center distance to reduce output variation, improving shading uniformity and dynamic range.

Initial signal connection lines and via-linked grid routing cut voltage drop across OLED display substrates and improve picture uniformity.

Embedded protective films between segmented OLED emitters guide and confine light upward, raising extraction efficiency without reducing aperture ratio.

Varying micro-lens dead zones by color filter keeps light in the correct pixel, reducing shadows and channel differences.

A segmented contact hole through stacked insulating layers preserves electrode connection while reducing pixel-area loss and improving PPI.

A gate-connected protection diode and opposite-type pickup improve MOS ESD robustness beyond larger layouts while preserving chip area.

A three-region RC IGBT layout separates forward and reverse current paths to cut current density and improve turn-off robustness.

A ferroelectric and anti-ferroelectric domain switching layer creates negative capacitance to break the 60 mV/dec limit and lower logic voltage.

A self-turn-on avalanche SCR with a parallel Zener chain improves HV ESD robustness while reducing IC area, capacitance, and false triggering.

Different branch-electrode pretilt angles let one TFT drive multiple sub-pixels, reducing LCD color shift while improving aperture ratio.

Different microlens curvatures matched to each color spectrum improve light extraction and viewing angle in electro-optical displays.

A high-index refractive layer and baffle walls redirect and block stray light to prevent false excitation and improve display color accuracy.

A patterned flat-layer layout improves via alignment and electrical connection in micro LED drive backplanes while cutting mask steps and resistance.

Edge-positioned contact portions preserve electrical connection while reducing light blockage, improving luminous efficiency in display electrodes.

A hollow bendable region and matched insulation thickness help large LED driving substrates bend without connection wire breakage or wider splicing gaps.

Encapsulated lead lines and through-substrate vias protect display bonding connections from erosion while enabling narrower bezels.

Specific light wavelengths trigger nitric oxide release to inactivate pathogens on mucosal tissue while reducing cytotoxicity and inflammation.

Auxiliary data lines and direct electrode connections cut resistance and voltage drop, helping high-resolution displays keep uniform brightness.

A recessed protective layer aligns the OLED first electrode symmetrically to cut viewing angle color shift and keep color recognition consistent.

An outer edge electrode blocks edge-generated charges from leaking into the optical black region, preserving black reference accuracy and reducing noise.

A holographic layer combines microlens and color filtering to focus light onto CMOS pixels, boosting quantum efficiency and reducing cross-talk.

A boron-oxygen host layer improves charge mobility and triplet energy use in TADF-assisted OLED emission for higher efficiency and color purity.

A patterned doped layer creates channel openings that lower carrier barriers and cut SPAD leakage and dark current in image sensors.

Adhesive auxiliary layers stabilize a hydrophobic dummy pixel defining layer, preventing lifting and metal short circuits in OLED displays.

Conductive pattern overlap on the active layer improves light-emitting element orientation and bias, raising display emission efficiency.

Segmented conductive portions and unique electrode connections cut IR drop and power use while preserving Micro/Mini LED luminous efficiency.

A bridge circuit with optimized die-to-die interfaces extends SoC-to-HBM routing, enabling more HBM stacks without degrading high-speed signals.

Multiple metal-layer signal wires partially overlap between adjacent terminals, enabling denser display substrate routing without shorts or misalignment.

A spacer-backed conductive layer shields through holes during laser soldering, reducing circuit cracks and improving micro LED transfer yield.

A multilayer selective reflective film blocks 310 nm or shorter inspection light, hiding back wiring while protecting TFT characteristics.

A backside metalens shortens the optical path in germanium CMOS sensors, reducing spacer thickness and improving angular response.

A stepped insulating layer shapes the oxide TFT channel to constrain n+ diffusion and keep threshold voltage stable in short-channel devices.

Alternating PMOS and NMOS standard cells in stacked layers raise logic density and use substrate space more efficiently in 3D CMOS layouts.

A shared metal layer forms gate, source, drain, and storage capacitor parts in one mask step, cutting LTPO panel process complexity and cost.

Epitaxial lateral overgrowth and a substrate hole reduce threading dislocations while improving light emission and wavelength conversion.

A single silicon ROIC combines CQD SWIR photodiodes and microbolometers to avoid bump bonding, cut fabrication complexity, and improve thermal compatibility.

Shared P- and N-diode stripes cut die-to-die I/O ESD area, support finer micro-bump pitch, and reduce floating micro-bumps.

A gate-over-diffusion-break layout isolates active regions without extra wiring, preserving stress and improving PFET mobility.