SOI Resistive Element Layout for Stable Resistance and Low TCR
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Solution Overview
Problem
The reliability of semiconductor devices with resistive elements on SOI substrates is limited due to challenges in maintaining resistance values and temperature coefficients, particularly in miniaturization and manufacturing cost, as existing techniques struggle to optimize the thickness and impurity concentration of resistive elements without compromising performance.
Innovation Solution
The semiconductor device incorporates a resistive element formed on an SOI substrate with an epitaxial semiconductor layer, where the resistive element has specific regions with varying thickness and impurity concentrations to enhance resistance values while minimizing temperature coefficient changes, using a structure with semiconductor portions and a region without epitaxial growth, allowing for increased resistance without increasing the number of manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the resistive element is increased to maintain resistance values, then the resistance value is improved, but the area occupied by the resistive element increases
Solution Approach 1:
The patent applies local quality by creating a resistive element with non-uniform thickness distribution. Specifically, the resistive element has a first region with a first thickness and a second region with a second thickness different from the first thickness. This localized variation in thickness allows optimization of resistance values in specific areas without increasing the overall area of the resistive element, thereby resolving the contradiction between maintaining resistance stability and reducing area occupation.
2Reliability
If the impurity concentration in the resistive element is increased to optimize resistance values, then the resistance value is improved, but the temperature coefficient of resistance changes adversely
Solution Approach 1:
The patent implements local quality by establishing different impurity concentration distributions in different regions of the resistive element. The first region has a first impurity concentration and the second region has a second impurity concentration, where the impurity concentrations are differently distributed. This regional differentiation allows each region to contribute differently to the overall resistance characteristics, enabling optimization of resistance values while controlling the temperature coefficient of resistance through coordinated design of multiple regions with varying impurity profiles.
3Manufacturing precision
If the number of manufacturing steps is increased to optimize resistive element characteristics, then the manufacturing precision is improved, but the manufacturing cost increases
Solution Approach 1:
The patent applies the merging principle by integrating the formation of multiple regions with different thicknesses and impurity concentrations into a single continuous manufacturing process. The resistive element is formed as an integrated structure comprising the first region and second region in one process flow, rather than requiring separate fabrication steps for each region. This consolidation achieves complex resistive element characteristics with optimized precision while avoiding the cost increase that would result from multiplying discrete manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and miniaturization of semiconductor devices by maintaining resistance values and reducing temperature-dependent changes, while also reducing the area required for resistive elements and manufacturing costs.
Implementation Method 1
the semiconductor layer located in the first region has a first connecting portion on which the first semiconductor portion is formed, a second connecting portion on which the second semiconductor portion is formed, and an element portion located between the first connecting portion and the second connecting portion and on which the epitaxial semiconductor layer is not formed
Data Source
AI summary
Improving a reliability of a semiconductor device. A resistive element is comprised of a semiconductor layer of the SOI substrate and an epitaxial semiconductor layer formed on the semiconductor layer. The epitaxial semiconductor layer EP has two semiconductor portions formed on the semiconductor layer and spaced apart from each other. The semiconductor layer has a region on where one of the semiconductor portion is formed, a region on where another of the semiconductor portion is formed, and a region on where the epitaxial semiconductor layer is not formed.


