Split Charge Storage Node Spacer Process
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The trend towards miniaturization of semiconductor memory devices poses challenges in achieving high circuit density, lower operating voltages, and faster access speeds due to the need for small features with close spacing, which existing technologies struggle to address effectively.
Innovation Solution
The development of memory cells with two split sub-lithographic first poly gates and two split sub-lithographic charge storage nodes on a semiconductor substrate, utilizing spacer formation techniques to control the dimensions of these components, allowing for reliable formation of sub-lithographic charge storage nodes separated by a dielectric to prevent signal crossover.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography techniques are used to scale down device dimensions, then manufacturing process simplicity is maintained, but manufacturing precision deteriorates due to the resolution limit of lithography
Solution Approach 1:
The charge storage node is divided into two separate sub-lithographic charge storage nodes formed through sequential spacer formation processes. The first spacer defines a first sub-lithographic charge storage node, and the second spacer defines a second sub-lithographic charge storage node. This segmentation allows each node to be formed with precision beyond the lithography resolution limit while using standard lithography equipment.
Solution Approach 2:
Mandrel structures are formed in advance before the actual charge storage nodes. These mandrels serve as templates for subsequent spacer formation. The preliminary mandrel structures enable precise positioning and dimension control of the final sub-lithographic charge storage nodes through conformal spacer deposition, achieving dimensions smaller than the lithography resolution limit.
2Productivity
If device dimensions are scaled down to increase circuit density, then productivity is improved, but manufacturing precision deteriorates due to difficulty in forming small features with close spacing
Solution Approach 1:
Spacer structures serve as intermediary elements between the lithographically-formed mandrels and the final charge storage nodes. The spacers are formed through conformal deposition with controlled thickness, enabling precise dimensional control of the sub-lithographic features. This intermediary approach allows accurate feature spacing and dimensions to be achieved through deposition control rather than direct lithography patterning.
3Area of stationary object
If charge storage nodes are placed closer together to increase density, then area is reduced, but reliability deteriorates due to signal crossover between adjacent nodes
Solution Approach 1:
Dielectric material is selectively placed in the space between the two sub-lithographic charge storage nodes to provide electrical isolation. This local dielectric insertion ensures that each charge storage node is electrically isolated from its neighbor, preventing signal crossover while maintaining minimal spacing between nodes. The dielectric acts as an insulating barrier that preserves signal integrity in high-density configurations.
Data Source
AI summary
Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.