Component Carrier Frame Layout With Dummy Chips for Warpage Control
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Solution Overview
Problem
The embedding of silicon or ceramic chips into electrically insulating materials during chip embedding processes introduces inhomogeneities, leading to thermomechanical stress and warpage in component carriers due to differing coefficients of thermal expansion, which complicates further processing such as laser drilling.
Innovation Solution
A component carrier design incorporating a stack of alternating electrically conductive and insulating layers with embedded semiconductor elements and dummy components made of undoped silicon, strategically arranged to match the thermal expansion properties of the active and frame areas, reducing warpage and deformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If silicon or ceramic chips are embedded into electrically insulating materials during chip embedding processes, then functional electronic components are integrated into the component carrier, but inhomogeneities are introduced leading to thermomechanical stress and warpage due to differing coefficients of thermal expansion
Solution Approach 1:
The patent applies local quality by embedding dummy components specifically in the frame area surrounding the active area, rather than uniformly distributing components throughout. This creates localized compensation zones that address the thermal expansion mismatch problem in specific regions where warpage occurs, while maintaining the functional integrity of the active area with its high silicon ratio
Solution Approach 2:
The patent changes the material composition parameter by introducing dummy components made of materials with specific thermal expansion properties into the frame area. This modifies the average CTE of the frame area to better match the active area, thereby reducing thermal expansion mismatches and the resulting warpage during temperature cycling
2Productivity
If the component carrier is separated into active areas with functional components and frame areas without functional structures, then the active area achieves optimized functional performance, but the frame area exhibits higher CTE and orthotropic expansion behavior causing in-plane pressure load during cooling
Solution Approach 1:
The patent applies local quality by selectively modifying the frame area with dummy components while leaving the active area unchanged. This creates a localized compensation mechanism in the frame area that reduces the thermal expansion mismatch between frame and active areas, thereby reducing the in-plane pressure load transferred to the active area edges during cooling
Solution Approach 2:
The patent uses dummy components as a counterbalancing mechanism. These dummy components act as a counterweight to the thermal expansion forces generated by the frame area, compensating for the higher CTE and orthotropic expansion behavior of the frame area materials, thereby reducing the net stress on the active area
3Manufacturing precision
If warpage is reduced by adding dummy components to the frame area, then manufacturing precision is improved, but device complexity increases due to additional components and arrangement optimization
Solution Approach 1:
The patent applies partial action by embedding dummy components only in the frame area rather than throughout the entire component carrier. This selective approach provides sufficient warpage compensation without the excessive complexity that would result from uniform distribution of dummy components across the whole structure
Solution Approach 2:
The patent uses dummy components as simplified copies or placeholders that replicate the thermal expansion characteristics of active components without providing full functionality. These dummy components serve as surrogates to balance the thermal forces, reducing warpage without requiring complex functional designs in the frame area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces warpage and deformation, allowing for easier processing of component carriers with high numbers of semiconductor elements by compensating for thermal expansion mismatches and preventing buckling, thereby enhancing the reliability of the processing steps.
Implementation Method 1
The properties of the embedded chips show a low CTE (coefficient of thermal expansion) combined with rather isotropic expansion, while behavior of the laminates show overall significantly higher CTE with an orthotropic expansion behavior
Implementation Method 2
At cooling down after pressing, this results in a situation where the overall thermal shrinkage of the frame area is higher than the shrinkage of the active area and thus an in-plane pressure load is applied to the edges of the active area
Data Source
AI summary
A component carrier may include a stack comprising a plurality of stacked layers, the stacked layers comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure; a plurality of equally designed electronic units formed in the stack, each electronic unit comprising at least one semiconductor element embedded into the stack, wherein each semiconductor element is made of a semiconductor material; wherein at least a plurality of said electronic units are arranged to form at least one active area, which is surrounded by a frame area without functional components; and a plurality of dummy components embedded into the stack in the frame area; wherein the at least a plurality of said electronic units is arranged in the at least one active area in a pattern comprising more than 2 rows and more than 2 columns.