Sub-Pixel Voting Lithography for Dual Damascene Fabrication
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Solution Overview
Problem
Current Dual Damascene processing methods for high-performance integrated circuits require multiple photoresist deposition and patterning steps, leading to increased costs and reduced throughput due to complex interconnect structure fabrication, particularly in Trench First and Via First techniques.
Innovation Solution
The development of sub-pixel voting lithographic patterning using a single layer of photoresist to generate recessed features with non-uniform cross-sectional geometries, allowing for simultaneous exposure and development of trench and via structures, reducing the need for multiple resist processing steps and enhancing processing flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photoresist deposition and patterning steps are used in Dual Damascene processing, then complex interconnect structures can be fabricated, but processing complexity and costs increase
Solution Approach 1:
The patent combines multiple patterning operations into a single photoresist layer by using overlapping exposure areas with different radiation intensities. The first area receives a first intensity to create one pattern, while the second area overlaps and receives a second intensity to create a different pattern, both in the same resist layer, eliminating the need for separate resist depositions and patterning steps.
Solution Approach 2:
The patent applies different radiation intensities to different areas of the same photoresist layer. The first area is exposed to a first intensity that produces a first pattern, while the second overlapping area is exposed to a second intensity that produces a second pattern. This local differentiation of exposure quality enables complex interconnect structures to be formed in a single resist processing step.
2Manufacturing precision
If multiple photoresist processing steps are used, then complex interconnect structures can be created, but throughput decreases
Solution Approach 1:
The patent merges multiple sequential patterning steps into a single parallel exposure process. By exposing different areas of the same photoresist layer to different radiation intensities simultaneously, the method creates complex interconnect structures in one step rather than requiring multiple sequential steps, thereby increasing manufacturing throughput.
Solution Approach 2:
The patent performs preliminary patterning actions in advance by exposing the photoresist layer to multiple different radiation intensities before development. This preliminary differentiation of exposure areas allows the complex interconnect structure to be defined in a single exposure step, eliminating the need for subsequent repatterning operations and improving throughput.
3Manufacturing precision
If traditional Dual Damascene methods are used, then interconnect structures can be fabricated, but the process requires multiple discrete processing steps increasing costs
Solution Approach 1:
The patent combines multiple discrete processing steps into a single integrated process by exposing different areas of one photoresist layer to different radiation intensities. This merging of operations eliminates the need for multiple resist depositions, patterning steps, and alignment procedures, thereby reducing fabrication costs while maintaining manufacturing precision.
Solution Approach 2:
The patent makes the single photoresist layer perform multiple functions by exposing it to different radiation intensities in different areas. The same resist layer simultaneously defines multiple patterns with different geometries and dimensions, replacing the need for multiple specialized processing steps and reducing overall fabrication complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication of complex interconnect structures, reducing complexity and costs, while improving throughput by enabling the creation of precise, non-uniform depth profiles in a single step, compatible with a wide range of materials and devices, including VLSI and ULSI systems.
Implementation Method 1
A first area of the layer of radiation sensitive material is exposed to radiation having a first intensity. A second area of the layer of radiation sensitive material is exposed to radiation having a second intensity
Data Source
AI summary
This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems. Processing methods of the present invention are capable of making micro- and nano-scale structures, such as Dual Damascene profiles, recessed features and interconnect structures, having non-uniform cross-sectional geometries useful for establishing electrical contact between device components of an electronic device. The present invention provides device fabrication methods and processing strategies using sub pixel-voting lithographic patterning of a single layer of photoresist useful for fabricating and integrating multilevel interconnect structures for high performance electronic or opto-electronic devices, particularly useful for Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication methods for making integrated electronics, and can be effectively integrated into existing photolithographic, etching, and thin film deposition patterning systems, processes and infrastructure.