Resistive Memory Structure for Stable Interconnect Height and RC Delay
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Solution Overview
Problem
Integration of resistive memory device processes with logic device processes leads to variations in interconnect structure height, resulting in unpredictable electrical performance due to varying resistive-capacitive delay (RC delay) in logic devices.
Innovation Solution
A resistive memory structure and manufacturing method that includes a substrate with a dielectric layer, a resistive memory device with a protrusion, a hard mask layer covering the variable resistance layer, and a spacer covering the sidewall of the variable resistance layer, ensuring the interconnect structure height is consistent across the logic device region, thereby maintaining expected electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If resistive memory device processes are integrated with logic device processes, then manufacturing efficiency is improved, but interconnect structure height varies causing RC delay variation
Solution Approach 1:
The resistive memory device is segmented into multiple functional layers (first electrode, variable resistance layer, second electrode) with distinct materials and thicknesses. This segmentation allows independent optimization of each layer's properties while maintaining overall structural integrity and consistent height with logic device interconnect structures.
Solution Approach 2:
Different regions of the resistive memory device are assigned different material properties and thicknesses tailored to their specific functions. The variable resistance layer has specific thickness and material composition to provide desired resistance characteristics, while electrode layers have optimized thickness for electrical connectivity, ensuring local quality optimization without compromising overall height consistency.
2Ease of manufacture
If variable resistance layer is exposed, then manufacturing simplicity is improved, but moisture damage occurs reducing reliability
Solution Approach 1:
A protective layer is introduced as an intermediary between the variable resistance layer and the external environment. This protective layer acts as a barrier that prevents moisture and contaminants from reaching the variable resistance layer, thereby improving reliability without significantly complicating the manufacturing process.
Solution Approach 2:
The resistive memory device employs a composite structure combining multiple materials with different properties. The variable resistance layer is combined with protective layers and electrode materials to create a composite structure that provides both functional performance and environmental protection, enhancing reliability while maintaining manufacturability.
Data Source
AI summary
Provided is a resistive memory structure and a manufacturing method thereof. The resistive memory structure includes a substrate, a dielectric layer, a resistive memory device, a hard mask layer, and a spacer. The dielectric layer is located on the substrate. The dielectric layer has an opening. The resistive memory device is located in the opening and has a protrusion outside the opening. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The hard mask layer covers a top surface of the variable resistance layer. The spacer covers a sidewall of the variable resistance layer in the protrusion.