CMOS Pixel Sensor Cells With Spacer Transfer Gates
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Solution Overview
Problem
CMOS image sensors with electronic global shutter operation face challenges in correlated double sampling and increased production costs due to the need for additional transistors, leading to noise issues and inefficiencies in charge transfer.
Innovation Solution
The implementation of spacer transfer gates in CMOS pixel sensor cells, which include a middle gate structure with insulation sidewalls and spacer transfer gates on either side, allowing for efficient charge transfer and correlated double sampling while maintaining a high-density 7T global shutter pixel design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 7T pixel sensor cell design is implemented to enable correlated double sampling and eliminate motion artifacts, then noise reduction and image quality improve, but chip area increases and production costs increase
Solution Approach 1:
The patent merges the transfer gate and hold gate into a single integrated structure where the hold gate serves dual functions. The poly gate structure is shared between transfer and hold operations, reducing the total transistor count from 7 to 5 while maintaining correlated double sampling capability and eliminating motion artifacts.
Solution Approach 2:
The hold gate structure is designed to perform multiple functions: it acts as both a transfer gate for moving charge from the photodiode and as a hold gate for storing charge during readout. This multi-functionality reduces the number of dedicated transistors needed while preserving the global shutter and CDS operations.
2Reliability
If additional transistors are added to achieve global shutter operation with correlated double sampling, then noise is reduced, but device complexity increases
Solution Approach 1:
The patent combines the transfer and hold gate functions into an integrated structure that uses fewer transistors. The poly gate is shared between transfer and hold operations, reducing the transistor count from 7 to 5 while maintaining the ability to perform correlated double sampling and global shutter operations for noise reduction.
3Reliability
If more transistors are used to implement 7T global shutter pixel, then correlated double sampling is enabled, but manufacturing cost increases
Solution Approach 1:
The patent merges transfer and hold gate functions into a single integrated structure, reducing the transistor count from 7 to 5. This reduction in transistor count directly lowers manufacturing complexity and production costs while preserving correlated double sampling capability through the shared poly gate structure.
4Reliability
If transfer gate charge transfer efficiency is increased to reduce noise, then more transistors are needed, but chip area increases
Solution Approach 1:
The patent combines transfer and hold gate functions into an integrated structure that maintains high charge transfer efficiency without requiring additional transistors. The shared poly gate structure enables efficient charge transfer from photodiode to floating diffusion while reducing the total chip area compared to separate transfer and hold gate implementations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances charge transfer efficiency, reduces noise, and increases pixel density, leading to improved image resolution and light sensitivity while minimizing production costs by eliminating the need for additional chip real estate.
Implementation Method 1
allowing the photodiode to convert the photons into electron/hole pairs
Data Source
AI summary
CMOS pixel sensor cells with spacer transfer gates and methods of manufacture are provided herein. The method includes forming a middle gate structure on a gate dielectric. The method further includes forming insulation sidewalls on the middle gate structure. The method further includes forming spacer transfer gates on the gate dielectric on opposing sides of the middle gate, adjacent to the insulation sidewalls which isolate the middle gate structure from the spacer transfer gates. The method further includes forming a photo-diode region in electrical contact with one of the spacer transfer gates and a floating diffusion in electrical contact with another of the spacer transfer gates.