Array Substrate Via-Hole Layout for Signal Uniformity and Aperture Ratio
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Solution Overview
Problem
The existing array substrates for high transmittance field switching liquid crystal displays with IGZO active layers face issues of uneven signals due to high resistance in the common electrode layer, particularly at high refresh rates and resolutions, which is exacerbated by the addition of via holes intended to reduce impedance, leading to a decrease in aperture ratio.
Innovation Solution
The array substrate design incorporates a via hole with a deep and shallow region, where the pixel electrode is connected to the drain in the deep region and the common electrode is connected to the compensation electrode through different parts of the via hole, reducing the number of via holes and improving the aperture ratio by allowing simultaneous connection between the pixel electrode and drain and the common electrode and compensation electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional via holes are provided to connect the compensation electrode to the common electrode layer, then the impedance and voltage drop of the common electrode layer are reduced, but the aperture ratio of the array substrate decreases
Solution Approach 1:
The patent merges the function of the via hole into the pixel electrode structure itself. The pixel electrode extends to form a via hole that penetrates the passivation layer, allowing the pixel electrode to directly contact the common electrode layer. This integration eliminates the need for separate additional via holes, thereby maintaining aperture ratio while achieving the compensation function.
Solution Approach 2:
The via hole structure serves multiple functions: it acts as both the pixel electrode extension for electrical connection and as the compensation electrode connection path. By making the via hole structure multi-functional, the patent avoids adding extra structures that would reduce aperture ratio, while still achieving impedance reduction and signal uniformity.
2Adaptability or versatility
If the common electrode layer is made large area to cover the display region, then the HFS display mode is realized, but the resistance of the common electrode layer increases causing uneven signals
Solution Approach 1:
The patent segments the common electrode layer into multiple regions connected through the pixel electrode via holes. Instead of relying on a single large-area continuous common electrode layer that causes resistance issues, the structure creates multiple connection points through which the common electrode layer is divided into electrically connected but physically segmented regions, reducing resistance and improving signal uniformity.
Solution Approach 2:
The pixel electrode via holes act as intermediaries that provide additional electrical connection paths between different regions of the common electrode layer. These intermediary connection structures reduce the overall resistance by creating parallel current paths, thereby improving signal uniformity across the large-area common electrode layer.
Data Source
AI summary
An array substrate includes a substrate, a gate layer, a source-drain layer, a first passivation layer, a common electrode layer, a second passivation layer, a pixel electrode layer, and a via hole penetrating at least the second passivation layer. The via hole has a deep hole region and a shallow hole region. A first part of the via hole in the deep hole region penetrates the second passivation layer and the first passivation layer, and a second part of the via hole in the shallow hole region penetrates the second passivation layer. In the deep hole region, a pixel electrode is connected to a drain, and in the shallow hole region, the common electrode layer is electrically connected to a compensation electrode through a first connection electrode and a second connection electrode.