Chip-on-Film Test Pad Layout for Multi-Chip Thin Bezels
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Solution Overview
Problem
The miniaturization and thinning of display apparatus bezels require increasingly complex chip on film packages with multiple semiconductor chips, necessitating innovative arrangements of test pads to maintain component size and functionality.
Innovation Solution
A chip on film package design featuring a film substrate with upper and lower layers, semiconductor chips, connection wirings, and test pads, where test pads are strategically positioned on the lower layer and connected via penetrating vias to optimize space usage and electrical connectivity between the display panel and driving printed circuit board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are mounted on a base film to achieve miniaturization and thinning of display apparatus, then the number of chips increases, but the component size and weight increase
Solution Approach 1:
The patent moves test pads from the upper layer to the lower layer of the base film, utilizing the third dimension (depth/thickness) to resolve spatial conflicts. This allows multiple semiconductor chips to be mounted on the upper layer while test pads are positioned on the lower layer, enabling miniaturization without increasing component weight
2Adaptability or versatility
If multiple semiconductor chips are mounted on a base film to achieve miniaturization and thinning of display apparatus, then the number of chips increases, but the component thickness increases
Solution Approach 1:
The patent utilizes the thickness dimension by positioning test pads on the lower layer of the base film rather than the upper layer. This vertical arrangement allows multiple chips to be integrated while maintaining thin profile, as test pads do not add to the overall thickness from the upper surface
3Device complexity
If test pads are positioned on the upper layer of the base film, then electrical connectivity is simplified, but space availability for chip arrangement is reduced
Solution Approach 1:
The patent resolves the space conflict by moving test pads to the lower layer of the base film, freeing up upper layer space for optimal semiconductor chip arrangement. Electrical connectivity is maintained through vertical connection structures that penetrate through the base film layers
Solution Approach 2:
The patent introduces connection structures (such as connection holes or vias) as intermediaries to bridge the lower layer test pads with the upper layer semiconductor chips. This mediator approach enables spatial separation while maintaining electrical connectivity
Data Source
AI summary
There is provided a chip on film package. The chip on film package includes a film substrate including an upper layer extending in first and second directions opposite to each other and a lower layer facing the upper layer, and having a cutting line formed thereon, first and second semiconductor chips disposed on the upper layer within an area of the cutting line, first and second connection wirings connected to the first and second semiconductor chips and extending toward the first and second directions, respectively, and a test pad connected to at least one of the first and second connection wirings and disposed on the lower layer, within the area of the cutting line.