Semiconductor Source-Line Layout With Shared Metal Power Lines
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Solution Overview
Problem
The existing semiconductor devices with metal source lines on a semiconductor source layer face challenges in reducing electrical resistance and optimizing the use of the metal layer for both source lines and power lines, leading to inefficiencies in voltage drop and power consumption.
Innovation Solution
The semiconductor device incorporates a metal layer that functions as both source lines and power lines, alternately arranged on the semiconductor source layer, reducing resistance by ensuring even distribution and connection through contacts, thereby minimizing voltage drop and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal layer is used only as source lines, then the electrical resistance of the source layer is reduced, but the metal layer cannot be used for other purposes (power lines)
Solution Approach 1:
The metal layer is configured to serve dual purposes: as source lines connected to the semiconductor source layer and as power lines connected to power supply terminals. This multi-functional design allows the same metal layer to provide both signal transmission and power distribution functions, resolving the contradiction between reducing electrical resistance and enabling versatile usage.
Solution Approach 2:
The source line function and power line function are merged into a single metal layer structure. By integrating both functions into one layer, the patent eliminates the need for separate metal layers for source and power distribution, thereby reducing overall resistance while maintaining adaptability for multiple purposes.
2Reliability
If separate metal layers are used for source lines and power lines, then each function is optimized, but the manufacturing complexity and stacked wiring layers increase
Solution Approach 1:
The patent combines source lines and power lines into a single metal layer, reducing the number of stacked wiring layers from two separate layers to one integrated layer. This merging approach maintains functional optimization for both source and power distribution while significantly simplifying the device structure and reducing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively lowers the resistance of the source layer, reducing voltage drop and power consumption by allowing the metal layer to serve dual purposes without increasing manufacturing complexity or stacked wiring layers.
Implementation Method 1
a metal layer 40...electrically connected to the first semiconductor layer...reduce electrical resistance of the entire source layer
Data Source
AI summary
A device includes a cell-array above transistors. A first semiconductor layer is above the cell-array and has a first surface on a side on which the cell-array is provided and a second surface opposite to the first surface. A first metal-wire is above the second surface and electrically connected to the first semiconductor layer. A second metal-wire is above the second surface to be present in the same layer as the first metal-wire and is not in contact with the first metal-wire and the first semiconductor layer. A first contact is below the first metal-wire, extends in a first direction from the first surface to the second surface, and electrically connects one of the transistors to the first metal-wire. A second contact is below the second metal-wire, extends in the first direction, and electrically connects another one of the transistors to the second metal-wire.