Semiconductor Cavity Sidewall Perpendicularity via Dry-Wet Etching

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Solution Overview

Problem

Existing backside illuminated (BSI) image sensor devices face challenges in downsizing due to tapered cavity profiles and rough surfaces, which limit sensing ability and affect light photo response quality.

Innovation Solution

A method involving a dry etching process to create a cavity with sloped sidewalls followed by a wet etching process to make the sidewalls perpendicular, increasing the volume and improving the surface quality of the heterogeneous radiation-sensing region, filled with germanium for enhanced light sensing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a dry etching process is used to create a cavity, then the cavity can be formed with controlled depth and shape, but the sidewalls become tapered and the surface becomes rough

Engineering Contradiction:
Improvecavity shape controlVSAvoidsidewall profile
Core Design Contradiction:
Manufacturing precisionVSShape

Solution Approach 1:

The etching process is segmented into two distinct stages: first a dry etching process to create the initial cavity with controlled depth, then a wet etching process to correct the sidewall profile. This segmentation allows each process to optimize for its specific function without compromising the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The wet etching process acts as an intermediary step that mediates between the dry etching process and the final cavity structure. It corrects the tapered sidewalls created by dry etching without removing excessive material, using selective chemical etching to achieve vertical profiles.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the cavity volume is increased to improve light sensing ability, then more light can be detected, but the device size and complexity increase

Engineering Contradiction:
Improvelight sensing abilityVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The methodology changes the etching parameters by switching from a purely dry etching process to a combined dry-wet etching sequence. This parameter change enables better control over cavity volume and shape, maximizing light sensing ability while maintaining manageable device dimensions.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances the light sensing ability and photo response quality by increasing the volume of the radiation-sensing region and reducing surface roughness, addressing the limitations of tapered profiles and crystal defects in existing BSI devices.

Implementation Method 1

performing a dry etching process upon the front surface of the substrate to form a cavity with sloped sidewalls

Methodology Applied
Scientific EffectDry etching:

Implementation Method 2

performing a wet etching process upon the front surface of the substrate to further etch the sidewalls of the cavity to be perpendicular to the front surface of the substrate

Methodology Applied
Scientific EffectWet etching:

Data Source

PatentUS10121805B2Semiconductor structure and method for manufacturing the same
Publication Date: 2018.11.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10121805B2 patent drawing
  • US10121805B2 patent drawing
  • US10121805B2 patent drawing

AI summary

A semiconductor structure is disclosed. The semiconductor substrate includes: a front surface and a back surface; and a heterogeneous radiation-sensing region in the semiconductor substrate, the heterogeneous radiation-sensing region including a top surface, a bottom surface and sidewalls, the top surface being adjacent to the front surface of the semiconductor substrate, the sidewalls being perpendicular to the front surface of the semiconductor substrate, and the bottom surface being parallel to the front surface of the semiconductor substrate. An associated manufacturing method is also disclosed.