Three-Electrode Capacitor Structure for Higher Capacitance Density
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Solution Overview
Problem
Current planar MIM capacitors in integrated circuits have low density and capacitance per unit semiconductor area due to their planar layout, and existing undulating MIM capacitors with complex finger elements face manufacturing difficulties and poor contact resistance.
Innovation Solution
A three-electrode capacitor structure with a planar bottom electrode, a middle electrode featuring spaced conductive pillars, and an upper electrode that undulates over these pillars, along with insulator layers, is developed to increase capacitance density. The structure includes a copper bottom electrode, an aluminum middle electrode, and a silicon nitride insulator layer, allowing for higher capacitance within a smaller area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar MIM capacitor layout is used, then manufacturing is simple, but capacitance density and capacitance per unit area are low
Solution Approach 1:
The patent transitions from a planar two-dimensional capacitor layout to a three-dimensional structure by introducing vertical conductive pillars that extend upward from the substrate. The upper electrode undulates over these pillars, creating additional capacitive surfaces in the vertical dimension. This dimensional transformation increases the effective capacitance area without proportionally increasing the footprint area, thereby improving capacitance density while maintaining compatibility with standard fabrication processes.
Solution Approach 2:
The patent embeds multiple conductive pillars within the capacitor structure, with the upper electrode undulating over and between these pillars. This nested arrangement allows the electric field to interact with multiple conductive surfaces vertically stacked within a compact volume, effectively nesting capacitive elements one above another to achieve higher capacitance density in a confined space.
2Quantity of substance
If undulating MIM layers with contacts to ends are used, then capacitance density is improved, but contact resistance is poor
Solution Approach 1:
The patent divides the middle electrode into multiple discrete conductive pillars rather than using a continuous undulating layer. Each pillar is independently formed and contacted, allowing for optimized contact interfaces at the base of each pillar. This segmentation enables better electrical contact to the middle electrode while maintaining the undulating upper electrode surface that provides high capacitance density.
3Quantity of substance
If finger-based MIM capacitors are used, then capacitance density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs an undulating upper electrode surface that curves and waves over the conductive pillars, replacing the complex straight-line finger patterns with a continuous curved surface. This curvature approach achieves high capacitance density through increased surface area in a compact footprint while being more compatible with standard deposition and patterning processes than finger-based structures.
Data Source
AI summary
A capacitor structure for an integrated circuit (IC) and a related method of forming are disclosed. The capacitor structure includes three electrodes. A planar bottom electrode has a first insulator layer thereover. A middle electrode includes a conductive layer over the first insulator layer and a plurality of spaced conductive pillars contacting the conductive layer. A second insulator layer extends over and between the plurality of spaced conductive pillars and contacts the conductive layer. An upper electrode extends over the second insulator layer, and hence, over and between the plurality of spaced conductive pillars. A length of the upper electrode can be controlled, in part, by the number and dimensions of the conductive pillars to increase capacitance capabilities per area.