Patterned Doped Channel Layout for Low-Dark-Current SPAD Sensors
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Solution Overview
Problem
The etching processes used in the fabrication of single photon avalanche diodes (SPADs) can damage semiconductor substrates, leading to defects that result in unwanted leakage currents and dark current issues, which reduce the performance of image sensors.
Innovation Solution
An image sensor integrated chip design featuring a patterned doped layer between different semiconductor materials, where the second semiconductor material extends through channel openings in the patterned doped layer to contact the substrate, reducing the barrier height and minimizing leakage currents while maintaining high performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If etching processes are used to fabricate SPADs, then device structure is formed, but substrate damage occurs leading to increased leakage currents and dark current
Solution Approach 1:
A patterned doped layer is introduced as an intermediary component between the substrate and the second semiconductor material. This doped layer acts as a mediator that protects the substrate from damage during etching processes while enabling proper device formation. The doped layer absorbs the harmful effects of etching on the substrate and provides a controlled interface that reduces leakage currents and dark current.
Solution Approach 2:
The doped layer is applied in a patterned manner rather than uniformly across the entire substrate. This localized doping creates specific regions with different electrical properties, allowing the structure to maintain low leakage currents in critical areas while still enabling device fabrication in other regions. The patterned approach ensures that the protective function is provided exactly where needed without affecting overall device performance.
2Object-generated harmful factors
If a doped layer is added between substrate and second semiconductor material, then leakage currents are reduced, but device complexity increases
Solution Approach 1:
The doping concentration and pattern of the doped layer are carefully controlled and optimized to achieve the desired reduction in leakage currents. By adjusting doping parameters such as concentration, depth, and spatial distribution, the layer provides effective leakage suppression without requiring excessive structural complexity. The parameter optimization allows a relatively simple additional layer to deliver significant performance improvement.
3Productivity
If channel openings are created in the patterned doped layer, then carrier transfer efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patterned doped layer is divided into distinct regions with channel openings that segment the structure into functional zones. These segmented channels provide dedicated pathways for carrier transfer, improving efficiency by directing carrier flow through specific routes. The segmentation approach allows for optimized carrier transport while the regular pattern provides natural alignment references that reduce manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases dark current and leakage currents, enhancing the performance of the image sensor integrated chip by providing a low barrier for electron-hole pair generation and transfer, thus improving photodiode efficiency.
Implementation Method 1
Image sensors operate according to the photoelectric effect, a phenomenon by which electrons-hole pairs are generated when incident light strikes an atom within a semiconductor body.
Data Source
AI summary
The present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material region. A second semiconductor material region is disposed onto the substrate. A patterned doped layer is arranged between the substrate and the second semiconductor material region. The second semiconductor material region includes a sidewall connecting to a bottom surface of the second semiconductor material region. The sidewall extends through the patterned doped layer. A bottom surface of the second semiconductor material region is directly over the photodiode region.