Charge Trap Memory Array Using BTB Readout for Multi-Bit Storage
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Solution Overview
Problem
Conventional NAND flash memory limits storage density to a single bit per memory cell, hindering further cost reduction and storage capacity enhancement.
Innovation Solution
The implementation of a memory array with charge trap flash transistors, where each memory cell has two independently programmable sites (BT1 and BT2) and selection transistors, allowing for simultaneous programming and reading of data bits using band-to-band tunneling current, and an erase scheme utilizing Fowler-Nordheim tunneling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional NAND flash memory stores only a single bit per memory cell, then the memory cell structure remains simple, but storage density is limited and cost reduction is hindered
Solution Approach 1:
The memory cell is segmented into multiple independently programmable sites (first programming site and second programming site) within the charge trapping layer, allowing each site to store separate data bits. This segmentation enables multi-bit storage per cell without requiring additional cells, thereby increasing storage density while maintaining a relatively simple cell structure.
Solution Approach 2:
The patent utilizes the vertical dimension of the charge trapping layer to create multiple programming sites at different locations (e.g., different depths or regions within the layer). By exploiting this spatial dimension, the memory cell can store multiple bits of data in a single cell volume, effectively increasing storage density without expanding the cell footprint.
2Quantity of substance
If multiple data bits are stored per memory cell using multiple programming sites, then storage density increases, but reading and programming complexity increases
Solution Approach 1:
The patent employs dynamic control of selection transistors to selectively activate specific memory cells and programming sites during read and programming operations. By dynamically enabling or disabling access to different sites through control gates and selection transistors, the system can independently program and read specific bits without interference, simplifying the overall operation despite multiple storage sites.
Solution Approach 2:
Selection transistors and control gates serve as intermediaries between the control circuitry and the multiple programming sites within each memory cell. These intermediary elements enable selective access to specific sites, allowing the control circuit to program or read individual bits without having to simultaneously manage all sites, thereby reducing operational complexity.
3Measurement precision
If band-to-band tunneling current is used for reading data, then read margin is improved, but energy consumption increases
Solution Approach 1:
The patent employs periodic or pulsed application of high voltages to generate band-to-band tunneling current only when needed for reading operations. By applying the tunneling voltage in short pulses rather than continuously, the system achieves sufficient read margin through the high-current tunneling effect while minimizing overall energy consumption by limiting the duration of high-power operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables higher storage density and improved read margin by allowing independent programming and sensing of multiple data bits per memory cell, enhancing storage capacity and reducing costs.
Implementation Method 1
allowing for simultaneous programming and reading of data bits using band-to-band tunneling current
Implementation Method 2
an erase scheme utilizing Fowler-Nordheim tunneling
Data Source
AI summary
A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.