I/O Output Circuit Layout for Latch-Up Noise Suppression
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Solution Overview
Problem
Semiconductor integrated circuit devices face a significant challenge in controlling the latch-up phenomenon caused by noise, particularly in the I/O cells, as existing configurations with ESD protection diodes and resistive elements fail to adequately mitigate noise propagation from pads and substrates.
Innovation Solution
The configuration includes an output circuit with an external output terminal, a first output transistor, a first ESD protection diode connected to the terminal, and a first protection resistance placed between the transistor and the diode, formed as separate resistance regions, with taps supplying power supply voltage to the substrate or well between these regions, effectively attenuating and absorbing noise before it reaches the output transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single resistive element is placed between the output transistor and the ESD protection diode, then ESD protection is provided, but noise propagation through the well and substrate cannot be sufficiently controlled
Solution Approach 1:
The protection resistance is divided into multiple separate resistance regions (first protection resistance region, second protection resistance region, etc.) instead of using a single continuous resistive element. These segmented resistance regions are positioned at different locations between the output transistor and the ESD protection diode, creating multiple noise attenuation paths that effectively control noise propagation through the well and substrate while maintaining ESD protection functionality
Solution Approach 2:
Different resistance regions are positioned at specific locations within the well region to address local noise propagation issues. The first protection resistance region is positioned closer to the output transistor while the second protection resistance region is positioned closer to the ESD protection diode, with each region providing localized noise attenuation in its respective area
2Area of stationary object
If the output transistor is placed close to the ESD protection diode for compact layout, then device area is reduced, but noise from the external terminal directly affects the output transistor
Solution Approach 1:
Multiple protection resistance regions are introduced as intermediary elements between the output transistor and the ESD protection diode. These resistance regions act as mediators that attenuate noise signals traveling from the external terminal through the ESD protection diode before they can reach the output transistor, while still allowing the compact layout to be maintained
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively controls the propagation of noise that causes latch-up, enhancing the noise resistance of semiconductor integrated circuit devices and preventing latch-up occurrences.
Implementation Method 1
the first protection resistance is placed between the first output transistor and the first ESD protection diode... noise applied to the external output terminal is attenuated by the first protection resistance
Implementation Method 2
taps supplying a power supply voltage to a substrate or a well are formed between the resistance regions... noise applied to the external output terminal is absorbed through the taps
Data Source
AI summary
In an output circuit of a semiconductor integrated circuit device, an output transistor is placed apart from an ESD protection diode connected to an external output terminal, and a protection resistance is placed between them. The protection resistance is formed as a plurality of separate resistance regions, and taps supplying a power supply voltage to a substrate or a well are formed between the resistance regions. Noise applied to the external output terminal is attenuated by the protection resistance before reaching the output transistor and absorbed through the taps.