Domain Switching Layer for Sub-60 mV/dec Logic Switching
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Solution Overview
Problem
The scaling down of silicon-based transistors is limited by high power density and the inability to lower operating voltage below 0.8 V, due to a subthreshold swing (SS) value of about 60 mV/dec, which restricts further device miniaturization.
Innovation Solution
A logic switching device utilizing a combination of ferroelectric and anti-ferroelectric materials with different crystalline phases and doping concentrations, integrated in a domain switching layer to achieve a negative capacitance effect, reducing the subthreshold swing and enhancing control efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If silicon-based transistors are scaled down, then device miniaturization is achieved, but power density increases and operating voltage cannot be lowered below 0.8 V
Solution Approach 1:
The patent changes the fundamental parameter of subthreshold swing from the conventional 60 mV/dec limit to below 60 mV/dec by introducing a negative capacitance effect through a domain switching layer. This parameter change enables operating voltages below 0.8 V while maintaining device functionality, thereby resolving the contradiction between device scaling and power density control.
Solution Approach 2:
The patent employs a composite domain switching layer comprising both ferroelectric and anti-ferroelectric materials with different crystalline phases (orthorhombic and tetragonal). This composite structure generates the negative capacitance effect that enables sub-60 mV/dec subthreshold swing, allowing transistor scaling without excessive power density increase.
2Use of energy by stationary object
If operating voltage is lowered to enable scaling, then power consumption decreases, but subthreshold swing limit of 60 mV/dec prevents voltage reduction below 0.8 V
Solution Approach 1:
The patent fundamentally changes the subthreshold swing parameter from the thermionic emission-limited 60 mV/dec to below 60 mV/dec through negative capacitance. This parameter transformation enables operating voltages below 0.8 V while maintaining adequate on/off current ratios, thus reducing power consumption without sacrificing voltage control capability.
Solution Approach 2:
The patent replaces the conventional thermionic emission mechanism that limits subthreshold swing with a electrostatic field-effect mechanism enhanced by negative capacitance. This substitution of the underlying physical mechanism enables breakthrough below the 60 mV/dec barrier, allowing lower operating voltages and reduced power consumption.
3Ease of manufacture
If conventional silicon-based transistors are used, then manufacturing maturity is maintained, but subthreshold swing cannot be reduced below 60 mV/dec
Solution Approach 1:
The patent uses a composite domain switching layer with ferroelectric and anti-ferroelectric materials that can be integrated into existing CMOS manufacturing processes. The specific combination of materials with different crystalline phases enables sub-60 mV/dec subthreshold swing while maintaining compatibility with standard semiconductor fabrication techniques, thus achieving improved manufacturing precision without sacrificing manufacturing maturity.
Solution Approach 2:
The patent introduces the domain switching layer as a localized functional component between the gate electrode and channel, rather than requiring fundamental changes to the entire transistor structure. This local quality enhancement approach allows sub-60 mV/dec performance to be achieved in specific regions while maintaining overall manufacturing process compatibility and maturity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively lowers the subthreshold swing below 60 mV/dec, enabling more efficient voltage amplification and improved switching characteristics, thereby facilitating the scaling down of transistors and enhancing device performance.
Implementation Method 1
A logic switching device utilizing a combination of ferroelectric and anti-ferroelectric materials with different crystalline phases and doping concentrations, integrated in a domain switching layer to achieve a negative capacitance effect, reducing the subthreshold swing and enhancing control efficiency.
Data Source
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AI summary
Provided are a logic switching device and a method of manufacturing the same. The logic switching device may include a domain switching layer adjacent to a gate electrode. The domain switching layer may include a ferroelectric material region and an anti-ferroelectric material region. The domain switching layer may be a non-memory element. The logic switching device may include a channel, a source and a drain both connected to the channel, the gate electrode arranged to face the channel, and the domain switching layer provided between the channel and the gate electrode.