Buried Word Line Isolation Structure for Dense DRAM Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices with buried gate structures face challenges in manufacturing and performance due to reduced size and increased integration density, leading to issues with electrical isolation and leakage current between storage contacts.
Innovation Solution
The implementation of an insulating structure with its bottom surface extending into the gate cap layer of a word line, enhancing electrical isolation between storage contacts of capacitors, and simplifying the fabrication process to improve reliability and performance in high-density memory units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of DRAM unit is reduced and integration density is increased, then the miniaturization requirement is met, but electrical isolation between storage contacts deteriorates and leakage current increases
Solution Approach 1:
The insulating structure transitions from a surface-level isolation approach to a deep-subsurface approach by extending into the gate cap layer, utilizing the vertical dimension to achieve isolation without increasing lateral footprint. This dimensional transition enables effective isolation in miniaturized structures where lateral spacing is insufficient.
Solution Approach 2:
The insulating structure is formed to extend into the gate cap layer before storage contacts are fabricated, establishing a pre-configured isolation barrier that prevents leakage current pathways from forming during subsequent processing and operation.
2Ease of manufacture
If conventional insulating structures are used in miniaturized DRAM, then fabrication is simpler, but leakage current between adjacent storage contacts occurs
Solution Approach 1:
The insulating structure acts as an intermediary element positioned between adjacent storage contacts, extending into the gate cap layer to block electrical leakage pathways while maintaining compatibility with existing fabrication processes.
3Reliability
If the insulating structure bottom surface is located in the gate cap layer, then electrical isolation is enhanced, but fabrication precision requirements increase
Solution Approach 1:
The gate cap layer serves dual functions as both the protective capping structure for the word line and as the isolation medium for adjacent storage contacts. The insulating structure utilizes this existing layer for isolation, eliminating the need for separate deep isolation structures and reducing precision requirements.
Data Source
AI summary
A semiconductor memory device includes a substrate, at least one word line, a plurality of bit lines and a plurality of insulating structures. The word line is disposed in the substrate, extends along a first direction, and includes a gate cap layer. The bit lines are disposed on the substrate and respectively extend along a second direction. The bit line crosses the word line, and includes a conductive layer. The insulating structures are disposed on the word line and respectively disposed between the bit lines. The bottom surface of the insulating structure is located in the gate cap layer. The area of the top surface of the insulating structure is larger than the area of the bottom surface of the insulating structure.