3D Memory Cell Stack Alignment Using Split Select Gates
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Solution Overview
Problem
The increasing number of memory cell stacks in three-dimensional semiconductor memory devices leads to misalignment issues and deteriorated operational reliability due to alignment challenges in the manufacturing process.
Innovation Solution
The semiconductor memory device incorporates a first and second select gate structure with a sub-block insulating layer in between, along with conductive patterns and channel structures that include inflection points to secure alignment margins, enhancing the manufacturing process and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cell stacks is increased to improve integration degree, then the degree of integration is improved, but misalignment between patterns occurs more easily and operational reliability deteriorates
Solution Approach 1:
The select gate structure is divided into a first select gate structure and a second select gate structure separated by a sub-block insulating layer. This segmentation allows independent formation and alignment of each gate structure, reducing cumulative alignment errors when increasing the number of memory cell stacks.
Solution Approach 2:
A sub-block insulating layer is introduced as an intermediary element between the first and second select gate structures. This insulating layer serves as a reference layer that facilitates precise alignment and positioning of adjacent memory cell stacks, thereby maintaining manufacturing precision even as the number of stacks increases.
2Quantity of substance
If the number of memory cell stacks is increased to improve integration degree, then the degree of integration is improved, but operational reliability deteriorates
Solution Approach 1:
By segmenting the select gate into separate first and second structures with an insulating layer between them, each segment can be independently optimized and controlled, reducing the propagation of defects and maintaining operational reliability across a larger number of memory cell stacks.
Solution Approach 2:
The sub-block insulating layer acts as a mediator that electrically isolates adjacent select gate structures, preventing interference and signal crosstalk between neighboring memory cell stacks. This ensures stable operation and maintains reliability even as the density of stacks increases.
3Manufacturing precision
If inflection points are added to channel structures to improve alignment margin, then alignment margin is improved, but device complexity increases
Solution Approach 1:
Inflection points are introduced into the sidewalls of the channel structures, creating curved surfaces that provide self-alignment features. These curved surfaces naturally guide the alignment process during manufacturing, improving alignment margin without requiring complex external alignment mechanisms.
Data Source
AI summary
Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a sub-block insulating layer interposed between a first select gate structure and a second select gate structure, a plurality of conductive patterns stacked over first and second select gate structures to be spaced apart from each other, and a channel structure penetrating one of the first and second select gate structures and the plurality of conductive patterns, the channel structure including an inflection point located at a level between the sub-block insulating layer and the plurality of conductive patterns.