Buried Gate Transistor Layout for Lower CMOS Sensor Noise
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Solution Overview
Problem
The capacitance generated between the fin portion of the gate electrode and the drain region in CMOS image sensors increases noise in amplified pixel signals, degrading the sensor's characteristics.
Innovation Solution
A semiconductor device with a field-effect transistor featuring a gate electrode with a buried gate portion that includes a first site and a second site with a thickness from the surface smaller than the first site, reducing the overlapping area and capacitance between the source and drain regions and the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fin portion is added to the gate electrode to improve control over the channel, then the transistor's switching performance is improved, but the capacitance between the gate electrode and drain region increases causing noise
Solution Approach 1:
The gate electrode is segmented into a plane portion and a fin portion that extends into the semiconductor substrate. This segmentation allows the gate to control the channel more effectively while the fin portion's specific geometry helps manage capacitance effects.
Solution Approach 2:
The gate electrode has different geometries at different locations: a plane portion at the surface and a fin portion extending downward. This local quality variation optimizes both channel control and capacitance management by having the fin portion interact with the channel while the overall structure limits unwanted capacitive coupling.
2Power
If the gate electrode is extended deeper into the substrate to improve channel control, then the transistor's on-state current is improved, but the overlapping area with source/drain regions increases causing higher capacitance
Solution Approach 1:
The gate electrode extends in the vertical dimension (depth into substrate) rather than only in the horizontal plane. This dimensional change allows improved channel control through better vertical field effect while the horizontal projection area remains limited, reducing overlapping area with source and drain regions.
Data Source
AI summary
An imaging device and a semiconductor device that can reduce the capacitance of a gate electrode are provided. The imaging device includes a photoelectric conversion element and a semiconductor device that reads charge generated by the photoelectric conversion element. The semiconductor device includes a semiconductor substrate and a field-effect transistor provided on the first surface side of the semiconductor substrate. The field-effect transistor includes a gate electrode including a buried gate portion buried from the first surface of the semiconductor substrate toward an inside of the semiconductor substrate, a gate insulating film disposed between the semiconductor substrate and the gate electrode, a source region provided on the semiconductor substrate and connected to one side of the gate electrode in a gate length direction of the gate electrode, and a drain region connected to the other side of the gate electrode in the gate length direction. The buried gate portion includes a first site, and a second site located between at least one of the source region and the drain region and the first region, and having a thickness from the first surface smaller than that of the first region.