LTPO Array Substrate Layout With Single-Mask Gate and Capacitor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The production process of low temperature polysilicon oxide (LTPO) display panels is complex and costly due to the requirement of multiple photomask processes, particularly 13 to 17 processes, which increases fabrication costs and complexity.
Innovation Solution
An array substrate design that reduces the number of photomask processes by forming key components such as the first gate, source, drain, and storage capacitor using a single photomask process, along with a dual-gate structure for enhanced control and thermal resistance, thereby simplifying the fabrication process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple photomask processes (13 to 17 processes) are used to fabricate LTPO back panel with both LTPS and Oxide TFT devices, then the device performance and functionality are improved, but the production cost and process complexity increase significantly
Solution Approach 1:
The patent merges the fabrication processes for LTPS and Oxide TFT devices by using a shared metal layer (first metal layer 50) that is processed by a single photomask to form both the first gate, first source, first drain for the Oxide TFT, and the second gate for the LTPS TFT. This consolidation reduces the total number of photomask processes from 13 to 17 down to a significantly lower number, thereby reducing production cost and process complexity while maintaining the functionality of both device types
Solution Approach 2:
The first metal layer 50 serves multiple functions simultaneously: it forms the first gate electrode for the Oxide TFT, the second gate electrode for the LTPS TFT, and the lower polar plate layer for the storage capacitor. This multi-functional design allows a single metal layer and single photomask process to accomplish what previously required multiple separate processes, directly addressing the contradiction between device performance and process complexity
2Manufacturing precision
If multiple photomask processes are used to form gate structures and storage capacitors separately, then the manufacturing precision of each component is improved, but the production cost increases
Solution Approach 1:
The patent combines the formation of the first gate, first source, first drain, and lower polar plate layer into a single photomask process step using the first metal layer 50. This merging maintains manufacturing precision because all components are formed in the same process step with the same photomask alignment, while significantly reducing production cost by eliminating multiple sequential photomask processes
Data Source
AI summary
The present application provides an array substrate and a display panel. The array substrate includes a substrate, a polycrystalline silicon active layer, a first gate insulating layer, a first metal layer, a second gate insulating layer, and an oxide active layer. The oxide active layer includes a first channel region and first doped regions arranged on both sides of the first channel region; the first metal layer is processed by a single photomask process to form a first gate, a first source and a first drain spaced apart; the first gate is arranged directly below the first channel region; the first source and the first drain are respectively connected to the first doped regions on both sides of the first channel region, and the first source or the first drain extends along the direction away from the first gate, serving as a lower polar plate layer of the storage capacitor.