Shared-Stripe ESD Circuit Layout for Fine-Pitch Die-to-Die I/O

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing integrated circuit (IC) designs face challenges in efficiently managing electrostatic discharge (ESD) protection, particularly in die-to-die (D2D) input/output (IO) signals, due to significant area consumption by traditional diode layouts, which restricts the use of finer micro-bump pitches and increases the number of unnecessary micro-bumps, leading to inefficient layout and compatibility issues.

Innovation Solution

The implementation of shared stripe ESD protection circuits in a stripe geometry for D2D IO signals, where the p-tap anode stripe of P-diodes and n-tap cathode stripe of N-diodes are shared between diodes connected to pads, reducing the number of stripes and area usage, thereby optimizing the layout and supporting finer micro-bump pitches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional macro pad or ring geometry ESD protection circuits are used, then ESD protection is provided, but area consumption is significant

Engineering Contradiction:

ImproveESD protectionVSAvoidarea consumption

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple ESD protection functions into a shared stripe geometry structure. Multiple diodes share common p-tap anode stripes and n-tap cathode stripes, consolidating what would traditionally require separate macro pad or ring geometries into a unified shared structure, thereby reducing overall area consumption while maintaining ESD protection capability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared stripe structure serves multiple diodes simultaneously, making the ESD protection circuit multi-functional. The common stripes are reused across multiple protection paths, allowing a single structure to perform the protective function for multiple signal lines rather than requiring dedicated structures for each

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If traditional ESD protection layouts are used, then ESD protection is provided, but compatibility with finer micro-bump pitches is restricted

Engineering Contradiction:

ImproveESD protectionVSAvoidmicro-bump pitch compatibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The ESD protection circuit is segmented into modular diode units that can be independently configured. Each diode pair (P-diode and N-diode) forms a protectable unit, and these modular units can be arranged to match various micro-bump pitch requirements, enabling adaptability to finer pitches while maintaining protection functionality

Inventive Principle:

Principle #1Segmentation

3Adaptability or versatility

If more micro-bumps are used, then D2D IO signal connections are provided, but the number of floating micro-bumps increases

Engineering Contradiction:

ImproveD2D IO signal connectionsVSAvoidnumber of floating micro-bumps

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

Multiple D2D IO signal connections are merged into shared ESD protection stripes. Instead of having separate protection structures for each signal line that would require individual micro-bumps, the patent combines multiple signal lines to share common p-tap and n-tap stripes, reducing the total number of micro-bumps needed and eliminating floating micro-bumps

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the area required for ESD protection circuits by up to 50% compared to traditional macro pad or ring geometries, enabling compatibility with finer micro-bump pitches and reducing the number of floating micro-bumps, thus enhancing the efficiency and layout optimization of D2D IO signals.

Implementation Method 1

Electrostatic discharge (ESD) can be harmful to electronics. During an ESD event, charge is transferred from one object to another (e.g., from a person to an integrated circuit (IC)).

Methodology Applied

Scientific EffectElectrostatic Discharge: Electrostatic Discharge

Implementation Method 2

an example ESD protection circuit includes a first P+/N-well diode (P-diode) and a first N+/P-well (N-diode) arranged in a stripe geometry

Methodology Applied

Scientific EffectDiode conduction: Diode

Data Source

PatentUS20240429225A1Electrostatic discharge protection circuit for die-to-die input/output signals

Publication Date: 2024.12.26 INTEL CORP

AI summary

An integrated circuit device includes an electrostatic discharge (ESD) protection circuit comprising a plurality of P+/N-well diodes (P-diodes) and a plurality of N+/P-well (N-diodes) arranged in a stripe geometry, a p-tap anode stripe of the ESD protection circuit shared between a first P-diode and a second P-diode of the ESD protection circuit, and a n-tap cathode stripe of the ESD protection circuit shared between a first N-diode and a second N-diode of the ESD protection circuit. Other examples are disclosed and claimed.