TFT Array Pixel Structure Using High-k and Low-k Dielectrics
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Solution Overview
Problem
High-resolution, large-size TFT-driven display panels face challenges with short addressing time and high capacitance loading, leading to decreased charging time due to parasitic capacitance issues caused by misalignment in multi-layer metal processes.
Innovation Solution
A pixel structure is developed with a switching element and storage capacitor using high-k dielectric materials for improved transconductance and capacitance, along with a low-k dielectric layer for cross-over areas to reduce cross-over capacitance, maintaining consistent performance across varying metal layer alignments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multi-layer metal process is used to form gate and data lines, then device functionality is achieved, but parasitic capacitance increases due to overlapping layers and misalignment
Solution Approach 1:
The patent applies different dielectric materials with different properties to different regions of the device. High-k dielectric material is used in the TFT active area to maximize capacitance, while low-k dielectric material is used in the cross-over area to minimize parasitic capacitance. This local differentiation of material properties resolves the contradiction by optimizing each region for its specific function.
Solution Approach 2:
The patent introduces a low-k dielectric layer as an intermediary material between the gate line and source/drain lines in the cross-over area. This intermediary layer acts as a buffer that reduces the electromagnetic coupling and parasitic capacitance between the overlapping conductive layers, allowing the multi-layer structure to function while minimizing its harmful effects.
2Reliability
If high-k dielectric material is used in TFT and storage capacitor, then transconductance and capacitance are improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the high-k dielectric layer formation into the existing multi-layer manufacturing process. The high-k dielectric layer is deposited as part of the standard TFT fabrication sequence, combining the performance-enhancing feature with the existing manufacturing flow. This integration minimizes additional process steps while achieving improved transconductance and capacitance.
Solution Approach 2:
The patent selectively applies high-k dielectric material only in regions where it provides performance benefit (TFT gate dielectric and storage capacitor regions), rather than throughout the entire device. This localized application maintains manufacturing feasibility by limiting the use of specialized materials to critical areas only.
3Object-generated harmful factors
If low-k dielectric layer is added for cross-over areas, then cross-over capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent segments the dielectric structure into distinct regions with different properties: high-k dielectric in the active TFT area and low-k dielectric in the cross-over area. This segmentation allows each region to be optimized independently for its specific function, reducing cross-over capacitance without compromising TFT performance.
Solution Approach 2:
The patent addresses the cross-over capacitance problem by adding a dielectric dimension rather than changing the conductive pattern. By introducing a low-k dielectric layer in the vertical dimension at cross-over regions, the patent reduces parasitic capacitance without increasing lateral device complexity or altering the fundamental multi-layer conductive structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances storage capacitance and transconductance while reducing cross-over capacitance, thereby improving the overall performance and reliability of the display panel without increasing manufacturing costs.
Implementation Method 1
each pixel has a pixel electrode and a storage capacitor to store electric charges between the pixel electrode and a common line
Implementation Method 2
a first dielectric layer disposed on the gate electrode... the first dielectric layer having a dielectric constant equal to or higher than 8
Implementation Method 3
the presence of overlapping metal layers will result in parasitic capacitance between the source and gate and between the drain and gate of the TFT
Implementation Method 4
a third dielectric layer having a dielectric constant equal to or lower than 5... arranged to cross over each other over a low-k dielectric layer
Data Source
AI summary
A pixel structure for use in a display panel includes a switching element and a storage capacitor. The switching element has a drain electrode and a source electrode disposed on a high-k dielectric layer with k being equal to or higher than 8. The storage capacitor has a first capacitor electrode, a second capacitor electrode and a third capacitor electrode, wherein a passivation layer is disposed between the second an third capacitor electrodes and the high-k dielectric layer is also disposed between the first and second capacitor electrodes. The pixel structure also has a common line connected to the first capacitor electrode, a source line, and a gate line arranged such that the source line, the gate line and the common line may cross over each other over a low-k dielectric layer at a cross-over area where k is equal to or lower than 5.