Array Substrate Via Layout for Narrow-Bezel Display Bonding
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Solution Overview
Problem
Existing display technologies face challenges in reducing the frame width of display apparatuses due to exposed lead lines that are prone to erosion, affecting the reliability and longevity of the electrical connections between signal lines and driving circuits.
Innovation Solution
The array substrate design incorporates a base substrate with a display area divided into regular and bonding sub-areas, featuring thin film transistors, bonding pads, and lead lines that are unexposed and encapsulated by insulating layers, preventing exposure to air and water vapor, and using a via structure to connect the lead lines to bonding pads without direct contact with the base substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lead lines are exposed to enable electrical connection between signal lines and driving circuits, then electrical connectivity is achieved, but the lead lines become prone to erosion from air and water vapor, reducing reliability
Solution Approach 1:
The patent introduces an insulating layer as an intermediary substance between the lead lines and the external environment (air and water vapor). This insulating layer completely covers the lead lines, preventing direct contact with harmful environmental factors while still allowing the lead lines to perform their electrical connection function. The insulating layer acts as a protective mediator that resolves the contradiction between maintaining electrical connectivity and preventing erosion.
Solution Approach 2:
The insulating layer creates an inert protective environment around the lead lines, isolating them from the reactive external atmosphere containing oxygen and moisture. This inert barrier prevents oxidation and other chemical reactions that would otherwise occur between the exposed lead lines and environmental factors, thereby enhancing reliability without compromising electrical function.
2Length of stationary object
If frame width is reduced to create frameless display devices, then aesthetic appeal and compactness improve, but exposed lead lines become more vulnerable to erosion
Solution Approach 1:
By introducing the insulating layer as a protective intermediary, the patent enables frame width reduction without sacrificing reliability. The insulating layer mediates between the need for compact design and the need for protected electrical connections, allowing the lead lines to be closely positioned while still being shielded from environmental erosion.
Solution Approach 2:
The insulating layer creates a localized inert environment around each lead line, enabling the display apparatus to achieve narrow frame widths while maintaining connection longevity. This protective barrier allows aggressive miniaturization of the frame structure without exposing the electrical connections to harmful external conditions.
3Reliability
If insulating layers are added to encapsulate lead lines, then protection against erosion is achieved, but device complexity increases
Solution Approach 1:
The patent merges the insulating layer function with the existing base substrate structure. Rather than adding separate protective components, the insulating layer is integrated into the substrate architecture, forming a unified structure that provides both mechanical support and electrical protection. This merging approach achieves lead line protection while minimizing increases in overall device complexity.
Solution Approach 2:
The insulating layer serves multiple functions simultaneously: it provides electrical insulation, protects against environmental erosion, and maintains structural integrity. This multi-functionality reduces the need for additional separate protective components, thereby limiting the increase in device complexity while achieving comprehensive lead line protection.
Data Source
AI summary
An array substrate including a display area having a plurality of subpixels is provided. The plurality of subpixels includes a plurality of first subpixels in a display-bonding sub-area and a plurality of second subpixels in a regular display sub-area. The array substrate includes a plurality of thin film transistors on a first side of the base substrate and respectively in the plurality of subpixels. A respective one of the plurality of first subpixels includes a bonding pad on a second side of a base substrate; a lead line electrically connecting a respective one of a plurality of thin film transistors to the bonding pad; and a via extending through the base substrate. The lead line is unexposed in the array substrate. The lead line extends from the first side to the second side of the base substrate through the via, to connect to the bonding pad.