3D Storage Cell Structure for Higher-Density Memory Stacking

The patent transitions from a two-dimensional storage array to a three-dimensional stacked structure. Multiple storage layers are stacked vertically along the column direction, with each layer containing storage cells formed by alternating conductive and insulative strips. This vertical stacking enables significantly higher storage density by utilizing the third dimension (height direction) while maintaining compatibility with existing manufacturing processes.

The patent implements a nested structure where storage cells are formed within stacked layers. Each storage cell consists of semiconductor structures positioned between adjacent conductive strips, with insulative strips providing isolation. The layers are nested vertically, with lower layers serving as bit lines for upper layers, creating a compact nested architecture that maximizes storage density.

The patent divides the storage device into multiple discrete stacked layers, each containing conductive strips, insulative strips, and semiconductor structures. This segmentation allows each layer to be manufactured and positioned independently, simplifying the overall stacking process. The alternating pattern of conductive and insulative strips creates modular units that can be replicated across multiple layers.

The patent designs the stacked structure so that conductive strips in lower layers serve dual purposes: as word lines or bit lines for their own layer and as control gates for storage cells in upper layers. This multi-functionality reduces the total number of separate components needed, simplifying manufacturing while achieving high storage density.