Read-Only Memories TRIZ Cases

Separate gate-voltage loading paths for WL, TSG, and BSG drivers cut tunneling effects and improve TDDB reliability with limited area impact.

Continuous two-period sensing uses capacitive node coupling to improve threshold voltage reading accuracy without adding read delay.

Detecting wordline charging current lets control logic adjust bitline voltage and connection timing to protect non-volatile memory data integrity.

Localized semiconductor contact plugs and doped lines boost read and erase current in 3D vertical memory while preserving storage density.

Channel equalization before resumed program loops stabilizes NAND cell-string voltage, preserving data reliability and lowering power use.

Segmented 3D memory blocks use grouped channel strings and isolation walls to raise density while easing circuitry integration.

A vertically stacked ECRAM channel uses oxygen-vacancy control to cut gate voltage, reduce inter-cell interference, and enable denser NAND cells.

Alternating conductive and insulating stacks expand wiring space, cut resistance, and reduce capacitive coupling in dense semiconductor memory.

Multiple sensing reads at different times let page buffers compare cell counts and identify defective wordlines faster and more accurately.

An opposite-polarity mitigation pulse detraps electrons before programming, reducing FEFET disturb and restoring threshold voltage reliability.

Threshold-voltage-aware pre-program and erase voltages improve mixed SLC/QLC block erase reliability while limiting over-erasure.

Heating memory cells during or after write and read operations helps recover threshold voltage drift from P/E cycling and extend NAND flash life.

Defective bit lines are detected before program, erase, and read operations, cutting redundant column area while improving memory error handling.

Detecting wordline charging current lets control logic tune bitline voltage and connection timing, improving non-volatile memory read reliability.

Dual read sequences detect current-change timing to correct NAND flash read voltages and improve data reading accuracy.

A discharge path mimics unconnected memory-cell on-states so page buffer sensing can be verified with broader nonvolatile memory test coverage.

Separate bias levels for sense amplifier and data latches cut standby current in memory page buffers while preserving stored data.

Staggered floating gates and a wave-shaped erase gate cut EEPROM cross talk capacitance while keeping array macro size nearly unchanged.

Staggered switching groups cut peak current on memory conductive paths, preventing voltage drops and high-voltage control faults.

Dynamic read pass voltage tuning across shared erase blocks cuts read disturb and bit errors as cell thresholds shift over time.

Controlled discharge branches regulate bit line discharge speed to prevent voltage leaks and circuit abnormalities during memory operation.

Shared first and second latch sub-circuits in 3D NAND page buffers cut element count, peripheral circuit area, and manufacturing cost.

A stacked strip memory structure raises storage density beyond 2D scaling limits while easing 3D stacking complexity.

Control circuitry adjusts bias current to each memory cell path, compensating for capacitance and resistance variation during access and storage.

Bias lookup from bit-line current sweeps enables precise analog synapse weight tuning in memory arrays while cutting logic area and power.

Conditional negative substrate bias shortens NAND discharge time while preventing string select transistor breakdown during verify.

Using depletion-type memory and select transistors lowers read voltage differences in NAND storage, cutting power use while preserving data storage.

A combined NAND flash and DRAM layout addresses the tradeoff between fast data access and non-volatile data retention in one memory structure.

Different unselect voltages across word line zones limit erase disturb in unselected sub-blocks while preserving single-side GIDL erase accuracy.

Segmented conductive layers and a staggered pillar layout cut resistance and improve NAND memory access reliability.

Ge-As-Te memory material shifts threshold voltage to cut power while preserving read window and data integrity in dense, fast 3D cross-point arrays.

Calibration logic corrects memory temperature codes with mode-specific ratio and offset values to limit power-noise errors and cut calibration time.

Staggered access line activation recycles discharge energy through coupled lines and a reservoir capacitor to cut memory power and heat.

Periodic read calibration records the best flash read voltage in advance, cutting SSD retry latency while keeping data reads stable.

Sequentially programming divided bit groups cuts peak current and charge pump area while preserving flash programming verification reliability.

Layer-specific bias scaling in non-volatile memory narrows conversion range, improving ADC resolution, performance, and circuit area use.

Dynamic select-gate touch-up pulses use Vt and temperature data to keep threshold voltage in range and reduce memory errors.

Concurrent page refresh during memory writes limits capacitive-coupling disturbs and preserves data integrity in high-density arrays.

Sequentially tuning string resistance and select-transistor thresholds offsets bit line voltage drop to improve in-memory computing accuracy and efficiency.

Gate-induced drain leakage pre-charges 3D NAND channels during sub-block programming to limit disturbs and protect data integrity.

Segmented source plates enable selective sub-block erase in memory arrays, improving data management and retention without full-block erasure.

An isolation structure separates parallel channel layers in 3D memory to stabilize cell current and improve dense access reliability.

A tail current capacitor in the page buffer stabilizes NAND bitlines during sensing, improving read accuracy, precharge time, and read window.

Configurable current-to-voltage and ADC blocks let memory VMM arrays read one or two columns with tunable voltage range for efficient neural computation.

By moving the eFuse link into the active area beside the MOS transistor, this layout cuts cell area 11% while preserving programming reliability.

Adjustable waiting and conduction periods help memory cells pass reads despite power noise and power drop, improving data retrieval accuracy.

A parallel-programmed, series-read main and backup fuse structure prevents fail-to-write-1 errors while limiting eFuse area growth.

Latches and NOR gates compute weight-input products inside 3D flash memory, speeding MAC operations while cutting data-movement energy.

Embedded energy-release materials trigger confined exothermic heating to irreversibly erase nonvolatile memory without damaging nearby components.

Adjustable kick voltage and pulse duration improve GIDL-based erase efficiency in non-volatile memory while reducing programming errors.