Memory Erase Voltage Control for Mixed SLC and QLC Blocks
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in optimizing data erase conditions for both Single-Level Cell (SLC) and Quad-Level Cell (QLC) when both cell types are used in the same block, particularly due to mismatched threshold voltage distributions before and after rewrite operations.
Innovation Solution
The semiconductor memory device adjusts the pre-program and erase voltages based on the distribution pattern of threshold voltages, using a control circuit to determine the appropriate program mode and generate voltages accordingly, ensuring optimal erase operations for SLC and QLC cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed erase conditions are used for both SLC and QLC in the same block, then device complexity is reduced, but erase operation reliability deteriorates due to mismatched threshold voltage distributions
Solution Approach 1:
The patent segments the erase operation into multiple stages with different voltage conditions. The first erase operation uses initial erase conditions, and the second erase operation uses adjusted erase conditions. This segmentation allows optimized erase conditions for different cell types (SLC/QLC) without requiring completely separate configuration systems, thus resolving the contradiction between device complexity and erase reliability.
Solution Approach 2:
The patent implements dynamic adjustment of erase conditions based on the program mode history. The control circuit determines whether to apply first or second erase conditions based on whether the block was previously programmed in SLC or QLC mode. This dynamic adaptation ensures optimal erase reliability for each cell type while maintaining a unified device architecture.
2Reliability
If erase conditions are optimized for a specific program mode, then erase operation reliability is improved, but adaptability to different program modes deteriorates
Solution Approach 1:
The patent changes the erase voltage parameters based on the program mode history. Two different erase voltage conditions are defined: first erase conditions for blocks previously programmed in one mode, and second erase conditions for blocks previously programmed in another mode. The control circuit selects the appropriate parameter set based on the distribution pattern, achieving both optimized reliability and broad adaptability.
Solution Approach 2:
The patent implements a feedback mechanism where the control circuit determines the appropriate erase conditions based on the program mode history and threshold voltage distribution pattern. This feedback loop ensures that the erase operation is adapted to the specific state of the memory block, achieving both optimized reliability for each mode and overall adaptability across different program modes.
3Reliability
If pre-program voltage is applied before erase operation, then write distribution reliability is improved, but energy consumption increases
Solution Approach 1:
The patent applies a pre-program voltage to the word line before the erase operation to adjust the threshold voltage distribution. This preliminary action ensures that the erase operation produces the desired write distribution reliability. The pre-program step is conditionally applied based on the program mode history, balancing the energy consumption against the reliability improvement.
Solution Approach 2:
The patent conditionally applies pre-program voltage based on the determined program mode. The control circuit decides whether to apply the pre-program voltage and at what level based on the threshold voltage distribution pattern and program mode history. This selective parameter adjustment achieves write distribution reliability while minimizing unnecessary energy consumption.
Data Source
AI summary
A semiconductor memory device includes a bit line, memory transistors connected to the bit line, a source line connected to the transistors, a word line electrically connected to a memory transistor, a voltage generation circuit configured to generate voltages to be applied to the lines, and a control circuit configured to control the voltage generation circuit. The control circuit is configured to: upon receipt of a command for erasing data, determine: one of program modes that was previously used based on a distribution pattern of threshold voltages of the transistors, and one of the program modes to be used, and control the voltage generation circuit based on said one of program modes that was previously used and the program mode to be used to erase the data.