Memory Driver Gate Voltage Loading for TDDB Reliability
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Solution Overview
Problem
The performance degradation of drivers in memory systems, such as word line, top select gate, and bottom select gate drivers, is caused by a large gate-drain voltage difference due to the use of the same gate voltage, leading to tunneling effects and poor time-dependent gate breakdown performance.
Innovation Solution
A modified voltage loading circuit is implemented to provide different gate voltages to different drivers, such as the WL, TSG, and BSG drivers, using a voltage converter and source follower to avoid shared gate voltages and reduce the gate-drain voltage difference, thereby improving driver performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the same gate voltage is used for all drivers (WL, TSG, BSG), then the voltage loading circuit is simple, but the gate-drain voltage difference becomes large causing tunneling effects and poor time-dependent gate breakdown performance
Solution Approach 1:
The voltage loading circuit is segmented into multiple independent voltage loading paths, with each path dedicated to loading a specific driver (WL driver, TSG driver, BSG driver). This segmentation allows each driver to receive its own optimized gate voltage, preventing the large gate-drain voltage difference that causes tunneling effects while maintaining circuit functionality.
Solution Approach 2:
Different gate voltages are applied to different drivers based on their specific requirements. The WL driver receives a first gate voltage optimized for word line selection, while TSG and BSG drivers receive second gate voltages optimized for select gate operation. This local quality approach ensures each driver operates under optimal voltage conditions, improving time-dependent gate breakdown performance.
2Reliability
If different gate voltages are provided to different drivers, then tunneling effects are reduced and driver performance is improved, but the voltage loading circuit complexity increases
Solution Approach 1:
The voltage loading circuit is divided into separate voltage loading paths for different drivers. Each path includes its own voltage loading components and control logic, allowing independent voltage control for WL, TSG, and BSG drivers. This segmentation enables optimized voltage delivery to each driver without requiring a completely redesign of the entire voltage loading system.
Solution Approach 2:
The voltage loading circuit is designed with multi-functionality, where the same basic voltage loading structure can be reused for different drivers by adjusting control signals and voltage levels. This universal design approach allows the circuit to provide different gate voltages to different drivers while maintaining a consistent architectural framework, thereby limiting the increase in overall circuit complexity.
3Reliability
If a modified voltage loading circuit with separate drivers is implemented, then time-dependent gate breakdown performance is improved, but chip area increases
Solution Approach 1:
The voltage loading circuit is segmented into modular sections, each responsible for a specific driver. This modular segmentation allows for compact integration where each module can be optimized for its specific function while sharing common resources such as control logic and voltage generation structures, thereby minimizing the overall chip area required.
Solution Approach 2:
The voltage loading circuit employs a nested structure where smaller voltage loading units are integrated within larger driver circuits. For example, the voltage loading components for TSG and BSG drivers are nested within or integrated with the WL driver circuitry, allowing multiple functions to occupy overlapping or adjacent spatial regions, thus reducing the total chip area consumption.
Data Source
AI summary
Examples of the present application disclose a memory, a storage system and an electronic product. The memory comprises a control circuit, a voltage loading circuit, a first driver, and a second driver. The voltage loading circuit, in response to a block selection signal received by a control terminal, is configured to load a first voltage to a control terminal of the first driver through a first output terminal, and load a second voltage to a control terminal of the second driver through a second output terminal. Because starting voltages may be loaded by different output terminals, all the drivers do not share the same starting voltage any longer, and performance degradation caused by a tunneling effect is avoided. Therefore, based on the memory provided by the examples of the present application, the performance degradation of various drivers can be improved.