Wave-Shaped Erase Gate Layout for Low-Crosstalk EEPROM Arrays

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Solution Overview

Problem

Existing EEPROM arrays face issues with high cross talk capacitance and macro size, which affect the performance and efficiency of memory cells.

Innovation Solution

The array design incorporates rows of floating gates with staggered islands and wave-shaped erase gates and word lines, increasing the spacing between adjacent floating gates to reduce cross talk capacitance without enlarging the macro size of the memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If traditional linear floating gate arrangement is used, then device layout is simple, but cross talk capacitance between adjacent floating gates is high

Engineering Contradiction:

Improvecross talk capacitanceVSAvoidgate structure complexity

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The floating gates are arranged in a staggered asymmetric pattern rather than a linear symmetric arrangement. This asymmetry increases the spacing between adjacent floating gates, thereby reducing the capacitive coupling (cross talk) between them while maintaining compact overall device dimensions.

Inventive Principle:

Principle #4Asymmetry

Solution Approach 2:

The erase gate is designed with a wave-shaped curved structure instead of a straight linear form. This curvature allows the erase gate to follow the staggered arrangement of floating gates, enabling increased spacing between floating gates for reduced cross talk while maintaining effective erase coverage.

Inventive Principle:

Principle #14Spheroidality (Curvature)

2Object-affected harmful factors

If spacing between adjacent floating gates is increased to reduce cross talk capacitance, then cross talk capacitance decreases, but macro size of memory array increases

Engineering Contradiction:

Improvecross talk capacitanceVSAvoidmacro size of memory array

Core Design Contradiction:

Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The floating gates are arranged in multiple stacked layers (vertical dimension) rather than a single planar layer. This vertical stacking allows adjacent floating gates in different layers to be positioned closer in the planar view, reducing the macro area, while sufficient spacing is maintained in the vertical direction to reduce cross talk capacitance.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The floating gates are divided into multiple staggered islands or segments across different layers. This segmentation allows the memory array to achieve compact planar dimensions while maintaining adequate spacing between corresponding floating gate segments, thereby reducing cross talk without increasing macro size.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12573458B2Method for forming semiconductor structure with wave shaped erase gate

Publication Date: 2026.03.10 UNITED MICROELECTRONICS CORP

AI summary

A method for forming semiconductor structure with wave shaped erase gate, the method including the steps: forming a floating gate having staggered islands on a substrate, forming a erase gate having a wave shape on the substrate at a first side of the floating gate, and forming a word line having the wave shape on the substrate at a second side of the floating gate opposite to the first side.