Memory String Layout for Bit Line Voltage Drop Compensation
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Solution Overview
Problem
The classical Von Neumann computing architecture is bottlenecked by high power consumption and limited processing speed due to frequent data migration and limited memory bandwidth, especially with the rise of big data and artificial intelligence applications.
Innovation Solution
A semiconductor device with memory string groups and bit lines where string resistances and threshold voltages of top select transistors decrease sequentially along the bit line, compensating for bit line voltage drops to improve computing performance and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission is performed between separated memory and processor through data bus, then data migration is enabled, but power consumption increases and processing speed is limited
Solution Approach 1:
The patent merges memory and computing functions into a single integrated device structure, where memory strings are directly coupled with bit lines that can perform computing operations. This eliminates the need for separate processors and data buses, thereby reducing power consumption and improving processing speed by performing computations directly within the memory device.
Solution Approach 2:
The memory device is designed to perform multiple functions: it can store data in memory strings and simultaneously perform computing operations through bit lines coupled with select transistors. This multi-functionality allows the same hardware structure to serve both memory and processing needs, reducing the overhead of data migration between separate components.
2Productivity
If memory bandwidth is limited, then memory structure is simplified, but computing performance is greatly affected
Solution Approach 1:
The memory device is segmented into multiple memory string groups, each coupled with select transistors and bit lines. This segmentation allows parallel access to multiple memory strings simultaneously, effectively increasing the memory bandwidth available for computing operations and improving overall computing performance.
Solution Approach 2:
The patent introduces a hierarchical structure with memory strings arranged in groups along first and second directions, with bit lines coupled in specific patterns. This dimensional organization enables more efficient data access paths and increases effective bandwidth by allowing simultaneous operations across multiple dimensions of the memory array.
3Measurement precision
If string resistances are uniform across memory string groups, then manufacturing is simplified, but bit line voltage drops cause sensing errors
Solution Approach 1:
The patent implements local quality by assigning different threshold voltages to top select transistors in different memory string groups. Specifically, memory string groups closer to the first end of the bit line have higher threshold voltages, while those farther away have lower threshold voltages. This compensates for bit line voltage drops and ensures uniform sensing accuracy across all memory strings.
Solution Approach 2:
The patent changes the threshold voltage parameter of top select transistors based on their position along the bit line. By systematically varying this parameter, the invention compensates for the physical effects of voltage drops in the bit line, thereby maintaining consistent sensing performance across the entire memory array without requiring complex resistance matching.
Data Source
AI summary
The examples of the present disclosure disclose a semiconductor device and an operating method thereof and a system. The semiconductor device includes: a plurality of memory string groups each including at least one memory string; and a plurality of bit lines each coupled with a plurality of memory string groups arranged along a first direction; wherein string resistances corresponding to the plurality of memory string groups with which a same selected bit line of the plurality of bit lines is coupled decrease sequentially along a direction from a first end of the selected bit line towards a second end of the selected bit line; and the first end is a node where the selected bit line is coupled with a page buffer or a bit line driver.