3D Memory Channel Isolation Structure for Consistent Cell Current
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Solution Overview
Problem
The challenge of improving the integration and operational reliability of semiconductor devices, particularly in three-dimensional structures, is hindered by limitations in memory cell area and inconsistent cell current flow due to varying numbers of drain select transistors being turned on during access operations.
Innovation Solution
A semiconductor device design featuring a gate structure with alternating conductive and insulating layers, including select lines and wordlines, and channel layers isolated by an isolation structure, allowing for parallel sub-memory strings with different data storage capacities and compensating for cell current differences through adjustments in precharge voltage and evaluation period lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional stacked memory cell structures are implemented to improve integration, then device density increases, but manufacturing complexity and operational reliability challenges increase
Solution Approach 1:
The patent divides the memory structure into multiple sub-memory strings (first, second, and third sub-memory strings) with different configurations. Each sub-memory string contains a specific number of memory cells (e.g., 8T, 10T, 12T configurations), allowing independent optimization and simplified control of each segment while achieving high overall integration through vertical stacking.
Solution Approach 2:
The patent transitions from planar two-dimensional memory cell arrangements to three-dimensional vertically stacked structures. Multiple gate structures and channel layers are stacked in the vertical dimension, enabling significantly higher integration density without increasing the footprint area, while maintaining manageable operational complexity through selective activation of different sub-strings.
2Quantity of substance
If multiple drain select transistors are used in parallel sub-memory strings, then storage capacity increases, but cell current consistency deteriorates due to varying numbers of transistors being turned on
Solution Approach 1:
The patent applies different transistor configurations to different sub-memory strings based on their specific requirements. The first sub-memory string uses an 8T configuration, the second uses a 10T configuration, and the third uses a 12T configuration. Each configuration is optimized for its local function, with drain select transistors strategically placed to ensure consistent current flow characteristics specific to each string's capacity requirements.
Solution Approach 2:
The patent varies the number of transistors and their arrangement parameters across different sub-memory strings to achieve both high storage capacity and consistent current flow. By changing the transistor count parameter (8T, 10T, 12T) and the activation pattern of drain select transistors, the system maintains reliable current consistency while scaling storage capacity across parallel strings.
Data Source
AI summary
A semiconductor device includes a gate structure including a first select line, a second select line, a first wordline, a second wordline, and a third select line. The semiconductor device also includes a first channel layer passing through the second wordline and the third select line. The semiconductor device further includes a second channel layer passing through the first wordline and the first select line, the second channel layer connected to the first channel layer, and a third channel layer passing through the first wordline and the second select line, the third channel layer connected to the first channel layer. The semiconductor device additionally includes an isolation structure that isolates the second channel layer from the third channel layer.