3D Flash Computing-in-Memory Circuit for Fast Low-Energy MAC
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Solution Overview
Problem
Existing computing-in-memory technologies in 3D flash memory face challenges in improving computing speed and reducing energy consumption.
Innovation Solution
A computing-in-memory circuit is designed with latches and NOR gates, where each latch is coupled to a memory string in a memory array, and NOR gates perform multiplication operations on weight signals and external inputs, with logic circuits and power supply voltage ramping to enhance computing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data is read from memory and processed with ALU circuits, then computing accuracy is maintained, but energy consumption increases and computing speed decreases
Solution Approach 1:
The patent merges memory storage and computing operations into a unified architecture. Memory cells directly perform multiplication operations with input signals, eliminating the need to transfer data between memory and separate ALU circuits. This integration of storage and computation functions reduces energy consumption and accelerates computing by performing operations in-place within the memory array.
Solution Approach 2:
The patent replaces traditional mechanical/electronic data transfer mechanisms (reading data from memory to ALU) with a field-based computing approach. Weight signals are sensed directly from memory cells and multiplied with input signals through circuit operations performed at the memory location, substituting physical data movement with localized computational operations.
2Use of energy by moving object
If computing operations are performed outside memory, then data processing flexibility is improved, but energy consumption increases
Solution Approach 1:
The patent implements a universal computing-in-memory architecture where the same memory structure can perform both data storage and various computing operations. The memory array can store weight data and simultaneously perform multiplication operations with different input signals, providing multi-functionality without requiring separate processing circuits for each operation type.
3Productivity
If traditional memory architecture is used, then manufacturing simplicity is maintained, but computing efficiency decreases
Solution Approach 1:
The patent segments the computing function across multiple memory cells and strings, with each memory cell pair capable of performing independent multiplication operations. This segmentation allows parallel processing of multiple data points simultaneously, improving computing efficiency while maintaining a structure that can be manufactured using existing memory fabrication processes.
Data Source
AI summary
A computing-in-memory circuit including latches and NOR gates is provided. Each latch has a word line, a bit line, a complementary bit line, and first and second output ends. The bit line is coupled to a local bit line of one memory string in a memory array. The complementary bit line is coupled to a local complementary bit line of the memory string. The memory string includes storage units, each having a memory cell pair. The second output end provides a weight signal, sensed by the latch, from the memory cell. Each NOR gate has a first input end coupled to the second output end of the latch, a second input end receiving an external input signal, and an output end outputting a product of the weight and input signals.