3D NAND Memory Pillar Layout for Lower Resistance Access
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in optimizing the structure and manufacturing processes to enhance performance and reliability, particularly in NAND flash memory systems, which affect data storage efficiency and durability.
Innovation Solution
The semiconductor memory device incorporates a specific layer stack configuration with semiconductor and conductive layers, including a memory pillar and conductive members, to improve electrical connectivity and reduce resistance, while using a staggered layout of memory pillars and bit lines to optimize data storage capacity and access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional layer stack structure is used, then the manufacturing process is simpler, but the electrical connectivity and resistance performance are insufficient
Solution Approach 1:
The patent divides the conductive path into multiple segmented conductive layers (first conductive layer, second conductive layer, third conductive layer) separated by insulating layers. This segmentation allows each conductive layer to be optimized independently for electrical connectivity while maintaining overall structural organization, resolving the contradiction between improved electrical performance and structural complexity.
Solution Approach 2:
The patent employs a composite structure combining conductive layers with insulating layers in a stacked configuration. This composite approach enables simultaneous achievement of good electrical connectivity (through conductive layers) and electrical insulation (through insulating layers), improving reliability while managing complexity through systematic material composition.
2Productivity
If memory pillars are arranged in a conventional layout, then the manufacturing process is easier, but the data storage capacity and access speed are limited
Solution Approach 1:
The patent transitions from a conventional two-dimensional layout to a three-dimensional staggered arrangement of memory pillars and bit lines. Memory pillars are positioned at different heights and lateral positions, creating vertical and diagonal connectivity paths. This dimensional change increases data storage capacity and access speed by reducing interference between adjacent memory elements while maintaining manufacturability through systematic patterning processes.
Solution Approach 2:
The patent implements a nested structure where bit lines are positioned between memory pillars in a staggered configuration, and conductive layers are nested within the insulating layer structure. This nesting approach maximizes space utilization and creates multiple parallel data paths, improving productivity while following established semiconductor manufacturing patterning techniques.
3Reliability
If the layer stack has more conductive layers, then the resistance is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent introduces insulating layers as intermediary structures between conductive layers. These insulating layers serve as precise alignment references and isolation barriers, enabling accurate positioning of subsequent conductive layers. The intermediary insulating layers reduce the direct alignment difficulty between conductive layers, allowing multiple conductive layers to be stacked with controlled resistance while maintaining manufacturable precision.
Solution Approach 2:
The patent forms insulating layers between conductive layers as a preliminary step before depositing subsequent conductive layers. This preliminary action establishes precise positional references and isolation structures in advance, ensuring that subsequent conductive layer deposition can achieve the required alignment precision and resistance performance without increasing manufacturing difficulty.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a substrate; a layer stack disposed above the substrate in a first direction; a first conductive layer disposed between the substrate and the layer stack; a memory pillar including a semiconductor film, extending in the first direction, and penetrating the first conductive layer; and a first member disposed apart from the memory pillar in a second direction intersecting the first direction, extending in the first direction, and penetrating the first conductive layer. The layer stack has a structure in which a first semiconductor layer, a second semiconductor layer, a second conductive layer, and a third conductive layer are stacked in order from a side of the substrate. The first semiconductor layer covers an end portion of the semiconductor film in the first direction and an end portion of the first member in the first direction.