NAND Page Buffer Read Control for Wordline Current Variations
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in maintaining the reliability of stored data due to variations in wordline charging currents caused by varying states of memory cells, which can lead to degradation of memory cells and reduced data integrity.
Innovation Solution
A non-volatile memory device with a control logic circuit that detects wordline charging currents during a preset detection time, adjusts bitline voltage and connection control signals based on these currents and reference values to compensate for cell current variations, thereby improving data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wordline charging current is detected and bitline signals are adjusted based on memory cell states, then data reliability is improved, but device complexity increases
Solution Approach 1:
The control logic circuit detects wordline charging current during the wordline setup operation (before the develop and sensing operations) to determine the states of memory cells in advance. Based on this preliminary detection, the system adjusts bitline voltage control signals and bitline connection control signals proactively, preventing potential data integrity issues before they occur during the main read or program verify operation.
Solution Approach 2:
The system implements a feedback mechanism where the detected wordline charging current is used to dynamically adjust subsequent bitline control signals. The control logic circuit continuously monitors the charging current characteristics and modifies bitline voltage levels and connection timing based on the detected memory cell states, creating a closed-loop control system that adapts to varying memory conditions.
2Measurement precision
If detection time is extended to improve accuracy of wordline charging current measurement, then measurement precision is improved, but operation speed decreases
Solution Approach 1:
The system performs current detection for only a portion of the total wordline setup period, specifically during a preset detection time window that is shorter than the complete setup operation. This partial detection approach captures sufficient charging current characteristics to determine memory cell states without requiring the full setup time, thereby maintaining measurement accuracy while preserving operation speed.
Data Source
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AI summary
Provided are a non-volatile memory device and an operating method thereof. The non-volatile memory device includes a memory cell array comprising a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a page buffer unit comprising page buffers connected to the plurality of memory cells through the plurality of bitlines, and a control logic circuit configured to output at least one control signal to the page buffer unit for performing a read operation based on a read command and an address, the read operation comprising a wordline setup operation, a pre-charge operation, a develop operation, and a sensing operation. The control logic circuit is configured to detect a wordline charging current, adjust at least one of a bitline voltage control signal set after the wordline setup operation and a bitline connection control signal during the develop operation.