Memory Read Timing Control for Power-Noise-Prone Cells
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Solution Overview
Problem
Existing memory storage apparatuses face issues with power noise and power drop during the reading of signature cells, leading to failed readings of option cells despite successful signature cell reads.
Innovation Solution
A controller circuit adjusts the waiting and conduction periods for reading memory cells to ensure successful read passes, allowing for correct data retrieval by iteratively adjusting these periods until the memory cells achieve a read pass.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed waiting period and conduction period are used for reading signature cells, then the reading process is simple and fast, but power noise and power drop cause reading failures of option cells
Solution Approach 1:
The patent applies dynamics by making the waiting period and conduction period adjustable rather than fixed. The controller dynamically adjusts these time parameters based on reading results, transitioning from a static control system to a dynamic one that adapts to power fluctuations and reading conditions, thereby improving reliability without excessive complexity
Solution Approach 2:
The patent changes the time parameters (waiting period and conduction period) as variable controls. By modifying these temporal parameters based on reading success or failure, the system optimizes its operation under different power conditions, resolving the contradiction between simple fixed parameters and adaptive parameter adjustment
2Measurement precision
If waiting period and conduction period are extended to ensure read pass, then reading accuracy improves, but reading time increases
Solution Approach 1:
The patent implements feedback by continuously monitoring reading results and using this information to adjust waiting and conduction periods. When reading fails, the system extends the time parameters; when reading succeeds, it maintains or reduces them. This closed-loop control ensures accuracy while minimizing unnecessary time extension
Solution Approach 2:
The patent applies partial action by extending time parameters only when necessary (upon reading failure) rather than always using maximum time. This selective extension ensures accuracy when needed while avoiding excessive time consumption during successful reads
Data Source
AI summary
A memory storage device including a memory cell array and a controller circuit is provided. The memory cell array includes a plurality of first memory cells. The controller circuit is coupled to the memory cell array. The controller circuit is configured to adjust a first waiting period and a first conduction period and read data stored in the first memory cells according to the first waiting period and the first conduction period until the first memory cells achieve a read pass. When the controller circuit adjusts the first waiting period to a target waiting time length and adjusts the first conduction period to a target conduction time length, the first memory cells achieve the read pass.