Multi-Plane Non-Volatile Memory Cache Write Using Unused Page Buffer
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Solution Overview
Problem
In multi-plane flash memory devices, the time required for program operations is significantly influenced by data input time, and adding latch circuits for cache writing complicates the algorithm and increases the area of the page buffer circuit and memory chip, making it challenging to minimize program time effectively.
Innovation Solution
A non-volatile memory device with multiple planes employs a page buffer circuit of a plane not performing the program operation as a cache, using a data line mux and controller to transfer data between page buffer units, allowing for cache write operations without additional latch circuits, thereby optimizing program time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If latch circuits for cache writing are added to the page buffer, then program time is reduced, but the area of the page buffer circuit and memory chip increases
Solution Approach 1:
The page buffer of the non-selected plane is made to serve dual purposes: its original function for that plane's operations and an additional function as a cache buffer for the selected plane's program operations. This multi-functionality eliminates the need for dedicated latch circuits while reducing program time.
Solution Approach 2:
The non-selected plane's page buffer serves itself by being utilized as a cache resource during program operations on the selected plane. This self-service approach allows the system to optimize program time without adding external components or increasing circuit area.
2Loss of time
If latch circuits for cache writing are added to the page buffer, then program time is reduced, but the algorithm becomes more complicated
Solution Approach 1:
By making the page buffer multi-functional, the invention avoids the need for complex cache management algorithms. The existing page buffer structure and control logic are leveraged, maintaining algorithm simplicity while achieving cache write functionality.
Solution Approach 2:
The system utilizes the existing self-managing capabilities of the page buffer structure to perform cache operations, avoiding the need for additional complex control algorithms that would be required if dedicated latch circuits were implemented.
3Loss of time
If data input time is minimized using cache write method, then total program time is reduced, but additional latch circuits are required
Solution Approach 1:
The invention achieves cache write functionality by making the page buffer multi-functional, allowing it to serve as both a data buffer for its native plane and a cache buffer for program operations on the selected plane, thereby minimizing data input time without adding latch circuits.
Solution Approach 2:
The page buffer performs cache write operations by utilizing its own structure and control mechanisms, serving itself as a cache resource without requiring additional latch circuits or complex external control logic.
Data Source
AI summary
When performing a program operation, a non-volatile memory device comprising a multi-plane performs a cache write operation by employing a page buffer circuit of a plane that does not perform the program operation. A data line mux transfers an externally input first data to a page buffer unit of a plane, which will be programmed, according to a plane select signal, transfers a second data to a page buffer unit of a plane on which a program operation is not performed, while the program of the selected plane is performed, and after the first data is programmed, provides a data transfer path between one page buffer unit and the other page buffer unit according to a data transfer control signal.