Configurable I/O Blocks for Memory VMM Arrays and Precise ADC Readout
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Solution Overview
Problem
The development of high-performance artificial neural networks is hindered by a lack of adequate hardware technology, particularly in terms of energy efficiency and scalability, as existing CMOS-implemented synapses are bulky and digital supercomputers are costly and inefficient.
Innovation Solution
Utilizing non-volatile memory arrays as synapses in artificial neural networks, allowing for individual programming, continuous analog programming, and precise tuning of memory cells to store synapse weights, thereby eliminating the need for separate multiplication and addition logic circuits and enhancing power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If CMOS analog circuits are used for synapses to achieve low-precision analog computation, then energy efficiency is improved, but the size of each synapse becomes bulky
Solution Approach 1:
The patent replaces traditional CMOS analog circuit implementations of synapses with a memory-based architecture where synapses are implemented as memory cells (e.g., in crossbar arrays). This substitution eliminates the need for bulky analog computation circuits while maintaining the ability to perform analog multiplication operations through conductance values stored in memory cells, thereby reducing synapse size while preserving energy efficiency
Solution Approach 2:
The memory cells used to implement synapses serve multiple functions: they store weight values (conductance), perform multiplication operations through conductance-based current generation, and can be programmed and tuned. This multi-functionality eliminates the need for separate multiplication and addition logic circuits, reducing overall system complexity and area while maintaining computational capabilities
2Productivity
If digital supercomputers or graphics processing unit clusters are used to achieve high connectivity and computational parallelism, then computational capability is improved, but cost and energy efficiency worsen
Solution Approach 1:
The patent merges multiple computational functions (multiplication, addition, weight storage) into a single integrated memory-based architecture. The crossbar array structure allows simultaneous parallel multiplication operations across multiple memory cells while naturally summing results through Kirchhoff's current law, eliminating the need for separate adder circuits and achieving high computational parallelism with reduced energy consumption compared to digital systems
Solution Approach 2:
The system utilizes the physical properties of memory cells (conductance values) to automatically perform multiplication operations without requiring additional computational logic. The analog currents generated by memory cells based on their conductance values naturally compute the weighted sum, allowing the hardware to serve its own computational needs without external processing units, thereby achieving energy-efficient parallel computation
Data Source
AI summary
In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an output block coupled to the vector-by-matrix multiplication array to receive current from the columns of the array, the output block comprising a current-to-voltage converter to receive current from one or two columns and convert the current into a voltage, the current-to-voltage converter comprising one or more variable resistors configurable to adjust the range of the voltage; and an analog-to-digital converter to convert the voltage into digital bits.