Prism-like Insulator Semiconductor Device for High Integration Density
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Solution Overview
Problem
Current semiconductor devices face limitations in integration density, storage capacity, retention period, and electrical characteristics, particularly in three-dimensional memory cell arrangements, which hinder the development of high-capacity, reliable, and efficient memory solutions.
Innovation Solution
A semiconductor device with a prism-like insulator and multiple transistors connected in series, utilizing an oxide semiconductor with indium, aluminum, gallium, yttrium, or tin, and zinc, where the charge accumulation layer is positioned between insulators, enabling a three-dimensional memory cell arrangement with improved electrical characteristics and high integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cell arrangement is implemented, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements three-dimensional memory cell arrangement by stacking multiple memory cell strings vertically over a single block, transitioning from two-dimensional to three-dimensional spatial utilization. This allows multiple memory cells to be arranged in the vertical direction, significantly increasing integration density without proportionally increasing manufacturing complexity through standardized stacking processes
Solution Approach 2:
The memory device is divided into multiple independent memory cell strings, each containing a stack of transistors and charge storage regions. This segmentation allows parallel processing and fabrication of individual strings, reducing overall manufacturing complexity while enabling high integration density through vertical stacking
2Quantity of substance
If more transistors are integrated, then storage capacity is improved, but leakage current increases
Solution Approach 1:
The patent extracts the charge storage function from the transistor channel region by introducing separate charge storage regions (floating gates or charge trap regions) positioned adjacent to the channel. This separation allows the transistor to maintain its switching function while providing dedicated regions for charge retention, reducing leakage current through improved charge confinement
Solution Approach 2:
Charge storage regions act as intermediary structures between the control gate and the channel, mediating charge retention while isolating the channel from direct charge effects. This intermediary structure reduces direct coupling and minimizes leakage current paths while maintaining storage capacity
3Quantity of substance
If transistor size is reduced, then integration density is improved, but electrical characteristics deteriorate
Solution Approach 1:
The patent applies different material compositions and structural configurations to specific regions of the transistor: high-k dielectric materials in gate insulator regions, metal gates for improved control, and selectively doped source/drain regions. These localized quality enhancements maintain electrical characteristics even as overall transistor dimensions are reduced for higher integration density
4Duration of action of stationary object
If retention period is extended, then data storage reliability is improved, but leakage current increases
Solution Approach 1:
The patent implements charge storage regions with high charge retention capability that are pre-configured to hold charges for extended periods. These regions act as cushioning structures that prevent charge loss over time, extending retention period while the surrounding insulating structures prevent charge leakage paths, thereby reducing leakage current
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a highly integrated semiconductor device with large storage capacity, long retention period, low leakage current, small subthreshold swing value, and high reliability, enabling efficient data storage and retrieval.
Implementation Method 1
the gate insulator includes a first insulator, a second insulator, and a charge accumulation layer, and the charge accumulation layer is positioned between the first insulator and the second insulator
Data Source
AI summary
A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.