Memory Bit Line Defect Handling Without Redundant Columns
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Solution Overview
Problem
Existing memory systems face inefficiencies due to defective bit lines, which increase the bit error rate and hinder erase and program operations, and the management of these defects through redundant columns adds cost and area without optimal utilization.
Innovation Solution
A memory system with a controller that detects and manages defective bit lines during operations, adjusting program, erase, and read operations without redundant columns, using in-memory detection and correction techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant columns and lookup tables are used to manage defective bit lines, then defective bit line management capability is improved, but memory die size and cost increase
Solution Approach 1:
The memory system performs self-diagnosis by detecting defective bit lines during normal read operations using the existing read circuitry. The system automatically identifies and manages defective bit lines without requiring external intervention or additional management hardware, allowing the system to serve its own defect management needs.
Solution Approach 2:
The existing read circuitry is made multi-functional by enabling it to perform both normal data reading and defective bit line detection. The same circuit infrastructure is used for dual purposes: retrieving stored data and identifying defective bit lines, thereby eliminating the need for separate detection hardware.
2Reliability
If redundant columns are added to replace defective bit lines, then defect tolerance is improved, but manufacturing cost and area increase
Solution Approach 1:
The system automatically detects and manages defective bit lines during operation, eliminating the need for pre-managed redundant columns. The memory system serves its own defect management needs by identifying defective lines and adapting operations accordingly, rather than relying on manufacturing-time redundancy allocation.
Solution Approach 2:
The system dynamically identifies and adapts to defective bit lines during operation rather than using static redundancy allocated at manufacturing. The defect management approach transitions from a fixed, pre-determined redundancy scheme to a dynamic, operation-time detection and adaptation mechanism.
3Productivity
If defective bit lines are not properly managed, then memory operations proceed without additional overhead, but bit error rate increases
Solution Approach 1:
The system performs preliminary detection of defective bit lines during read operations before using the data. By identifying defective bit lines in advance during the read process, the system can prevent erroneous data from being used, thereby maintaining low bit error rates without requiring additional error correction overhead.
Solution Approach 2:
The system uses feedback from read operations to identify defective bit lines. The read circuitry provides feedback information about bit line status, which is then used to adjust subsequent operations and prevent errors, creating a closed-loop error prevention mechanism.
Data Source
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AI summary
Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines. In some examples, identification of open or shorted bit lines can be used to identify read operations involving those open or shorted bit lines as weak in connection with performing soft bit read correction.