3D Memory Wiring Stack Layout for Lower Resistance and Coupling
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in efficiently expanding wiring space and reducing wiring resistance and capacitive coupling due to the close proximity of conductive layers, particularly in the manufacturing process.
Innovation Solution
The semiconductor storage device employs a design with multiple conductive layers and insulating layers alternately stacked, incorporating a wiring layer with increased conductive paths and using heat-resistant metals for lower layers and low-resistance metals for upper layers to optimize wiring space and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conductive layers are stacked close together to increase storage capacity, then wiring space is limited and wiring resistance increases, but device complexity increases
Solution Approach 1:
The patent divides the conductive layers into different types: bit line conductive layers and word line conductive layers. By segmenting the wiring functions into separate layers, the design reduces capacitive coupling between adjacent conductors while maintaining high storage capacity through vertical stacking. This segmentation allows independent optimization of each layer's properties.
Solution Approach 2:
The patent introduces insulating layers as intermediaries between adjacent conductive layers. These insulating layers act as mediators that reduce capacitive coupling and electromagnetic interference between bit lines and word lines, enabling closer spacing of conductive layers while maintaining signal integrity and reducing wiring resistance.
2Quantity of substance
If conductive layers are stacked close together to increase storage capacity, then wiring space is limited, but device complexity increases
Solution Approach 1:
The patent designs the stacked conductive layers to serve multiple functions: storage capacity through vertical stacking, signal transmission through optimized conductive paths, and electromagnetic isolation through insulating layers. This multi-functionality allows the same structural element (stacked layers) to achieve both high capacity and reduced complexity by integrating multiple purposes into the wiring architecture.
Solution Approach 2:
The patent applies different properties to different regions: bit line conductive layers are optimized for data transmission with specific conductivity characteristics, while word line conductive layers are optimized for word selection with different geometric configurations. This local quality optimization allows each layer to be tailored for its specific function, reducing overall device complexity despite the multi-layer structure.
3Reliability
If heat-resistant metals are used in lower layers and low-resistance metals in upper layers, then wiring resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the material parameters of conductive layers based on their position and function: lower layers use heat-resistant metals with appropriate conductivity, while upper layers use low-resistance metals optimized for signal transmission. This parameter change strategy allows optimization of wiring resistance for each layer while managing manufacturing precision requirements through controlled material deposition processes tailored to each layer's specific requirements.
Data Source
AI summary
A semiconductor storage device includes a memory cell array including memory blocks having first conductive layers stacked in a first direction, the memory blocks extending in a second direction intersecting the first direction, and arranged in a third direction intersecting the first and second directions; and a first stacked structure including: a first region in which second conductive layers and first insulating layers are alternately stacked in the first direction, a second insulating layer extending in the first direction, a second region in which third conductive layers and third insulating layers are alternately stacked in the first direction, and a third region in which fourth insulating layers and the third insulating layers are alternately stacked in the first direction. The third region includes a first contact penetrating the fourth and third insulating layers.