NOR Flash Programming Control for Lower Peak Current
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Solution Overview
Problem
Existing NOR flash memory devices face challenges in reducing programming current during operations, which affects power consumption and manufacturing costs due to the area occupied by the charge pump circuit.
Innovation Solution
A flash memory device and programming method that dynamically adjust the number of bits programmed simultaneously and the programming time, dividing target bit groups into parts and applying programming voltage sequentially or simultaneously based on verification cycles to reduce peak programming current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a charge pump circuit is used to provide stable drain voltage to memory cells during programming, then programming reliability is improved, but the area occupied by the charge pump circuit increases proportionally with the peak programming current
Solution Approach 1:
The patent divides the bit group into multiple parts (first part, second part, third part) and programs them sequentially rather than simultaneously. This segmentation of the programming operation reduces the peak current demand on the charge pump circuit, allowing for a smaller charge pump circuit area while maintaining programming reliability through multiple verification cycles.
Solution Approach 2:
The patent implements dynamic programming time adjustment based on verification results. After the first programming operation, the system performs verification and adjusts the programming time for subsequent operations. This dynamic adjustment optimizes the balance between programming speed and current reduction, enabling smaller charge pump circuit area while maintaining reliability.
2Area of stationary object
If programming current is reduced to lower manufacturing cost, then the area occupied by charge pump circuit decreases, but programming time may increase
Solution Approach 1:
By segmenting the bit group into multiple parts and programming them sequentially with reduced current, the patent achieves smaller charge pump circuit area. The segmentation allows the system to complete programming through multiple cycles, accepting increased total time in exchange for reduced peak current and smaller circuit area.
Solution Approach 2:
The patent changes the programming time parameter dynamically based on verification results. After initial programming and verification, the system adjusts programming time for subsequent cycles, optimizing the balance between completing programming reliably and minimizing total time while using reduced current.
3Reliability
If multiple programming verification cycles are performed on target bit groups, then programming reliability is improved, but peak programming current increases
Solution Approach 1:
The patent segments the bit group into multiple parts and programs them one at a time across multiple verification cycles. This segmentation ensures that even when multiple verification cycles are performed, the peak current at any given time is reduced because only one part is being programmed at a time, not all bits simultaneously.
Solution Approach 2:
The system dynamically adjusts programming time and current based on verification results. After each verification cycle, the system determines whether additional cycles are needed and adjusts the programming parameters accordingly, optimizing the balance between reliability and peak current for each specific verification scenario.
Data Source
AI summary
A flash memory device and a programming method thereof are provided. The flash memory device includes a memory array and a memory control circuit. The memory array has a plurality of bit groups. The memory control circuit is configured to sequentially perform programming operations on the bit groups. The memory control circuit performs one or more programming verification cycles on a target bit group in the bit groups when the target bit group fails a programming verification, wherein the target bit group is divided into M parts, and M is a positive integer greater than 1. The memory control circuit determines whether the programming verification cycle performed on the target bit group is a first programming verification cycle. The memory control circuit sequentially programs the M parts with a first programming time when the first programming verification cycle is performed on the target bit group.