Semiconductor Memory Device Region Segmentation for Data Retention

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Solution Overview

Problem

As semiconductor memory devices become more integrated, their data retention characteristics degrade, leading to reduced refresh periods and the need for increased redundancy cells, which are inefficient, especially as device integration increases.

Innovation Solution

A semiconductor memory device with a cell array divided into regions of different memory characteristics, using a nonvolatile array for storing group information and conversion information to manage memory operations based on these characteristics, allowing for efficient address conversion and refresh management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If device integration is increased, then memory density is improved, but data retention characteristic deteriorates

Engineering Contradiction:
Improvememory densityVSAvoiddata retention characteristic
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The cell array is divided into multiple regions (first region, second region, third region) with different memory characteristics. Each region is managed separately with region-specific refresh periods and replacement policies, allowing the system to optimize for both high density and reliable data retention in different areas simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the cell array are assigned different memory characteristics and management strategies. The first region has shorter refresh period, the second region has medium refresh period, and the third region has longer refresh period, creating local optimization for data retention while maintaining high overall density.

Inventive Principle:
Principle #3Local quality

2Reliability

If refresh period is reduced, then data retention reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata retention reliabilityVSAvoidrefresh management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The refresh management is segmented into multiple regions with different refresh periods. Instead of implementing a single complex refresh mechanism for the entire array, the system uses simpler region-specific refresh strategies, reducing overall complexity while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The refresh period is made dynamic and adaptive based on region characteristics. The system automatically adjusts refresh timing for each region according to its specific memory characteristics, eliminating the need for complex manual refresh management while ensuring data retention reliability.

Inventive Principle:
Principle #15Dynamics

3Reliability

If redundancy cells are increased, then reliability is improved, but device complexity increases

Engineering Contradiction:
ImprovereliabilityVSAvoidredundancy management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The cell array is segmented into regions with different characteristics, and redundancy cells are strategically placed in specific regions rather than uniformly distributed throughout. This segmented approach reduces the total number of redundancy cells needed while maintaining reliability, and simplifies management by associating redundancy with specific functional regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Redundancy cells are allocated based on local requirements of each region. Regions with more variable or critical memory characteristics receive appropriate levels of redundancy, while regions with stable characteristics have minimal redundancy. This local quality approach improves reliability where needed without unnecessarily increasing overall device complexity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9058897B2Semiconductor memory device storing memory characteristic information, memory module and memory system having the same, and operating method thereof
Publication Date: 2015.06.16 SAMSUNG ELECTRONICS CO LTD
  • US9058897B2 patent drawing
  • US9058897B2 patent drawing
  • US9058897B2 patent drawing

AI summary

A semiconductor memory device includes a cell array including a plurality of regions accessed by first addresses, where the plurality of regions including at least two groups of regions having respectively different memory characteristics. The device further includes a nonvolatile array for nonvolatile storage of group information indicative of which of the least two groups each of the plurality of regions belongs.