3D Memory Array Block Layout for Density and Isolation
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Solution Overview
Problem
Existing memory array architectures face challenges in achieving high circuit density and cost efficiency, particularly in the formation of vertically-stacked memory cells and the integration of peripheral control circuitry, which affects the overall performance and scalability of memory arrays.
Innovation Solution
The method involves forming a stack of vertically-alternating conductive and insulative tiers with channel-material strings arrayed in sets and groups, where the channel-material strings are directly coupled to a conductor tier, and trenches are formed to create memory blocks with a wall for electrical isolation, allowing for efficient integration of memory cells and control circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-stacked memory cells are implemented to increase circuit density, then the number of memory cells per unit area increases, but the manufacturing complexity and integration difficulty of peripheral control circuitry increases
Solution Approach 1:
The memory array is divided into multiple independent memory blocks, each with its own peripheral control circuitry. This segmentation allows each block to be manufactured and integrated separately, reducing the overall manufacturing complexity while maintaining high circuit density through vertical stacking. The conductive tiers and channel-material strings are organized into discrete blocks that can be independently processed.
Solution Approach 2:
The patent transitions from planar memory cell arrangement to three-dimensional vertically-stacked architecture. Memory cells are stacked in the vertical dimension with multiple tiers separated by insulative layers, allowing significantly higher circuit density without proportionally increasing the lateral footprint or manufacturing complexity. The vertical stacking enables more memory cells to be integrated within the same chip area.
2Area of stationary object
If vertically-stacked memory cells with conductive tiers are formed, then space utilization improves, but the manufacturing precision requirements increase
Solution Approach 1:
Insulative tiers are formed between the conductive tiers in advance during the manufacturing process. These insulative layers serve as pre-formed structural elements that define the spacing and alignment requirements for subsequent conductive tier formation. By establishing the insulative framework first, the precision requirements for conducting material deposition are reduced, as the insulative tiers provide built-in alignment references and spacing control.
Solution Approach 2:
The insulative tiers act as intermediary layers between the conductive tiers, providing both electrical isolation and structural support. These intermediary insulative layers simplify the manufacturing process by serving as templates that guide the formation of conductive tiers, reducing the direct precision requirements between conductive elements. The insulative material acts as a buffer that accommodates minor variations in conductive tier positioning.
3Reliability
If memory blocks are separated by walls for electrical isolation, then device reliability improves, but the manufacturing process complexity increases
Solution Approach 1:
The wall structure serves dual functions: it provides electrical isolation between adjacent memory blocks (improving reliability) and simultaneously acts as a structural support element for the vertically-stacked memory cells (simplifying manufacturing). By combining the isolation function with the structural support function in a single integrated wall element, the manufacturing process is simplified compared to implementing separate isolation structures. The walls are formed as part of the overall memory block structure rather than as add-on components.
Data Source
AI summary
A memory array comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers and are arrayed in sets that are spaced from one another in horizontal X and Y directions. The channel-material strings in individual of the sets are arrayed in groups that are spaced from one another in the Y direction. Individual of the groups comprise multiple rows of the channel-material strings that are spaced from one another in the Y direction. Y-direction distance between immediately-adjacent of the groups is greater than Y-direction distance between immediately-adjacent of the rows within the individual groups. The stack comprises memory blocks that are spaced from one another in the Y direction. Immediately-adjacent of the memory blocks have a wall there-between that extends through the stack and is horizontally elongated in the X direction through multiple of the sets and through space that is between the individual groups in the individual sets. Methods are disclosed.