Non-Volatile Memory Programming via ISPP and Partial Verification
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Solution Overview
Problem
Current memory devices face inefficiencies in programming data, particularly in non-volatile memory cells, due to high internal current consumption and the need for multiple verification operations, which slow down data input/output speeds and increase power consumption.
Innovation Solution
The implementation of Incremental Step Pulse Programming (ISPP) and a current sensing circuit (CSC) to gradually increase threshold voltages in non-volatile memory cells, allowing for a single program pulse to reach higher threshold states, thereby reducing the number of verification operations and internal current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple verification operations are performed during programming, then data accuracy is improved, but internal current consumption increases and programming speed decreases
Solution Approach 1:
The programming process is divided into multiple stages with different verification strategies. Critical programming stages perform verification while less critical stages use simplified verification or none, segmenting the verification operations based on their importance to data accuracy.
Solution Approach 2:
Instead of performing full verification operations at every programming stage, the patent applies partial verification only where necessary. This reduces the total number of verification operations and associated current consumption while maintaining sufficient data accuracy through targeted verification at critical points.
2Reliability
If multiple verification operations are performed during programming, then data accuracy is improved, but programming speed decreases
Solution Approach 1:
Verification operations are segmented and distributed only to critical programming stages rather than applied uniformly across all stages. This segmentation maintains data accuracy at essential checkpoints while reducing overall verification overhead and improving programming throughput.
Solution Approach 2:
The patent implements partial verification at selective stages instead of exhaustive verification throughout the entire programming process. This approach achieves sufficient data accuracy while minimizing the time spent on verification operations, thereby improving overall programming speed.
3Manufacturing precision
If threshold voltage is gradually increased through multiple pulses, then programming precision is improved, but programming time increases
Solution Approach 1:
The threshold voltage adjustment process is segmented into discrete steps with verification at key transitions. This allows precise control of voltage changes while reducing total programming time by avoiding continuous incremental adjustments throughout the entire range.
Solution Approach 2:
Instead of applying numerous small incremental voltage pulses, the patent uses larger voltage steps combined with verification at critical points. This partial approach achieves sufficient programming precision while significantly reducing the number of pulses required and thus the total programming time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data input/output speed and reduces power consumption by minimizing the number of verification operations and internal current consumption during programming, improving overall memory device efficiency.
Implementation Method 1
applying program pulses to a group of non-volatile memory cells to gradually increase threshold voltages of the group of non-volatile memory cells from an erased state to a first programmed state
Implementation Method 2
a current sensing circuit (CSC) to check a threshold voltage distribution of non-volatile memory cells
Data Source
AI summary
A memory device includes a cell group and a control circuit. The cell group includes plural non-volatile memory cells, each capable of storing multi-bit data corresponding to plural program states and an erased state. The control circuit performs at least two partial program operations for programming the multi-bit data in at least two non-volatile memory cells. The at least two partial program operations include an ISPP operation to increase a threshold voltage of the at least two non-volatile memory cells from the erased state to a first program state among the plural program states and a single pulse program operation to increase a threshold voltage of at least one non-volatile memory cell among the at least two non-volatile memory cells from the first program state to another program state which is higher than the first program state among the plural program states.