NAND Memory Reading Sequence Control for Capacitive Coupling

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Solution Overview

Problem

In NAND-type memory devices, miniaturization leads to increased capacitive coupling between conductive lines, causing reading errors due to voltage swings, especially in multilevel memories where threshold voltage levels are closely spaced, resulting in incorrect cell state detection.

Innovation Solution

A reading method and device where the order of connecting the end terminals of cell stacks to reference and bitlines is determined based on the address of the selected cell, ensuring that the connection to the bitline occurs before or after charging, thereby minimizing capacitive coupling and preventing reading errors by maintaining the selected cell's wordline remote from the conductive line that is raised later.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the dimensions of NAND memory devices are reduced to minimize device size, then device miniaturization is achieved, but capacitive coupling between conductive lines increases causing voltage swings and reading errors

Engineering Contradiction:

Improvedevice sizeVSAvoidreading accuracy

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by determining the order of connecting end terminals to reference and bitlines based on the address of the selected cell before the actual read operation. This pre-determined sequencing ensures that connections are established in an optimal order that minimizes capacitive coupling effects before they can cause voltage swings and reading errors, thereby maintaining reading accuracy in miniaturized devices.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamics by making the connection sequence adaptive rather than fixed. The order of connecting end terminals is dynamically determined based on the specific address of the selected cell, allowing the system to optimize the connection sequence for each particular read operation. This dynamic approach enables the system to minimize capacitive coupling effects that vary depending on which cell is being accessed in the miniaturized memory structure.

Inventive Principle:

Principle #15Dynamics

2Ease of operation

If end terminals are connected to reference and bitlines in a fixed sequence, then device operation is simplified, but voltage swings occur due to capacitive coupling causing reading errors

Engineering Contradiction:

Improveconnection controlVSAvoidreading accuracy

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-determining the optimal connection sequence based on the selected cell's address before executing the read operation. This advance planning of the connection order allows the system to avoid voltage swings caused by capacitive coupling without adding complex real-time control logic during the actual read operation, thus maintaining ease of operation while improving reliability.

Inventive Principle:

Principle #10Preliminary action

3Length of moving object

If miniaturization is pursued to reduce memory device dimensions, then device size is minimized, but threshold voltage levels become closely spaced making cell state detection inaccurate

Engineering Contradiction:

Improvememory device dimensionsVSAvoidcell state detection accuracy

Core Design Contradiction:

Length of moving objectVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by establishing the optimal connection sequence in advance based on the selected cell address, before the actual voltage measurement for cell state detection occurs. This pre-determined sequencing minimizes capacitive coupling effects that would otherwise distort the threshold voltage measurements, thereby maintaining measurement precision even as device dimensions are reduced and threshold voltage levels become closely spaced.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents reading errors by controlling the sequence of terminal connections based on the cell address, reducing capacitive coupling and ensuring accurate voltage levels for cell state determination, even in multilevel memory configurations.

Implementation Method 1

NAND memory reading is usually based on charge integration and exploits the parasitic capacitance CP associated to each bitline 10

Methodology Applied

Scientific EffectParasitic capacitance: Parasitic Capacitance

Implementation Method 2

increased capacitive coupling due to component miniaturization may cause

Methodology Applied

Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS7349265B2Reading method of a NAND-type memory device and NAND-type memory device

Publication Date: 2008.03.25 STMICROELECTRONICS SRL

AI summary

A reading method of a NAND memory device includes the steps of first connecting a first end terminal of a stack of cells to a reference line, second connecting a second end terminal of the stack of cells to a respective bitline, and charging the bitline to a predetermined bitline read voltage, where one of the steps of first connecting and second connecting is carried out before charging the bitline and the other of the steps of first connecting and second connecting is carried out after charging the bitline. An order of carrying out the steps of first connecting and second connecting is determined based on an address of a selected cell.