3D NAND Page Buffer Latch Sharing to Reduce Peripheral Circuit Area
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Solution Overview
Problem
The increasing storage density in 3D NAND flash memory devices leads to a significant increase in the number of page buffers, occupying a large area in the peripheral circuit and increasing manufacturing costs.
Innovation Solution
The memory device incorporates a page buffer with at least two groups of latch circuits, each comprising a first and second latch sub-circuit, where the first latch sub-circuit latches first information on a sensing node, and the second latch sub-circuit latches second information through the first latch sub-circuit, with a pass control switch enabling information transfer between them, and a parasitic capacitor storing the second information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If storage density is increased in 3D NAND flash memory, then memory capacity is improved, but the number of page buffers increases occupying more peripheral circuit area
Solution Approach 1:
The patent combines two latch circuits (first latch circuit for to-be-written data and second latch circuit for read data) into a single shared latch structure. The same physical latch circuit is dynamically configured to store different types of data (to-be-written data during program operations or read data during read operations), thereby reducing the total number of latch circuits needed and decreasing peripheral circuit area occupation.
Solution Approach 2:
The latch circuit is designed with multi-functionality to serve dual purposes: it can store to-be-written data when needed for program operations and store read data when needed for read operations. This universal design allows a single latch circuit to replace what would traditionally require two separate latch circuits, reducing the peripheral circuit area while maintaining full functionality for both program and read operations.
2Quantity of substance
If the number of page buffers is increased to support higher storage density, then memory capacity is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the functionality of multiple page buffers into fewer physical structures by implementing shared latch circuits. Instead of providing separate latch circuits for every page buffer instance, the same latch circuit structure is shared across multiple page buffers through dynamic configuration, thereby reducing the total component count and associated manufacturing costs while supporting higher storage density.
Solution Approach 2:
The latch circuit is dynamically reused between different operational modes. During program operations, the latch circuit stores to-be-written data; during read operations, it stores read data. This dynamic recovery and reuse of the latch circuit for different purposes reduces the need for permanent dedicated structures, lowering manufacturing complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the number of elements in the page buffer, thereby reducing the chip area occupied by the page buffers and lowering manufacturing costs.
Implementation Method 1
the second latch sub-circuit comprises: a parasitic capacitor for storing the second information
Data Source
AI summary
The present application discloses a memory device, a memory system and an operation method, wherein the memory device includes a memory array including a plurality of memory cells; and a peripheral circuit coupled with the memory array and including a plurality of page buffers; each page buffer includes at least two groups of latch circuits; each group of latch circuits includes a first latch sub-circuit and a second latch sub-circuit; the first latch sub-circuit is coupled with a sensing node and configured to latch first information on the sensing node; and the second latch sub-circuit is coupled with the sensing node and configured to latch second information on the sensing node through the first latch sub-circuit, wherein the first information in the first latch sub-circuit and the second information in the second latch sub-circuit are switched through the sensing node.